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| Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet The Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported. Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is powered from a single 3.3V power supply. Applications Combination 10BASE-T/100BASE-TX Network Interface Cards (NICs) Wireless access points Network printers 10/100 Personal Computer Memory Card International Association (PCMCIA) cards Cable Modems and Set-Top Boxes Product Features 3.3V Operation IEEE 802.3-compliant 10BASE-T or 100BASE-TX with integrated filters Auto-negotiation and parallel detection MII interface with extended register capability Robust baseline wander correction Carrier Sense Multiple Access / Collision Detection (CSMA/CD) or full-duplex operation JTAG boundary scan MDIO serial port or hardware pin configurable Integrated, programmable LED drivers 48-pin Low-profile Quad Flat Package RESET_L ADDR[1:0] MDIO MDC Management / Mode Select Logic Power Supply Register Set Clock Generator VCC GND REFCLK/XI XO TX_EN TXD[3:0] TX PCS Manchester 10 Encoder Parallel/Serial Converter Scrambler 100 & Encoder Auto Negotiation Register Set OSP Pulse Shaper + TP Driver TP Out TPOP TPON - TX_CLK LED/CFG[3:1] JTAG 5 COL Collision Detect Clock Generator Media Select OSP Adaptive EQ with Baseline Wander Cancellation 100TX TDI TDO TMS TCK TRST_L + TP In TPIP TPIN RX_CLK RXD[3:0] RX P CS RX_DV CRS RX_ER Serial-toParallel Carrier Sense Converter Data Valid Error Detect 10 100 Manchester Decoder Decoder & Descrambler OSP Slicer 10BT + B3387-13 Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL (R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2005, Intel Corporation. 2 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Contents 1.0 Introduction to This Document ......................................................................................... 10 1.1 1.2 2.0 3.0 4.0 5.0 Document Overview ............................................................................................10 Related Documents............................................................................................. 10 Block Diagram for Intel(R) LXT972M Transceiver............................................................... 11 Pin Assignments for Intel(R) LXT972M Transceiver ...........................................................12 Signal Descriptions for Intel(R) LXT972M Transceiver ....................................................... 15 Functional Description...................................................................................................... 21 5.1 Device Overview .................................................................................................22 5.1.1 Comprehensive Functionality ................................................................. 22 5.1.2 Optimal Signal Processing Architecture ................................................. 22 Network Media / Protocol Support.......................................................................23 5.2.1 10/100 Network Interface .......................................................................23 5.2.2 MII Data Interface ................................................................................... 25 5.2.3 Configuration Management Interface ..................................................... 25 Operating Requirements .....................................................................................28 5.3.1 Power Requirements ..............................................................................28 5.3.2 Clock Requirements ............................................................................... 28 Initialization.......................................................................................................... 29 5.4.1 MDIO Control Mode and Hardware Control Mode .................................31 5.4.2 Reduced-Power Modes .......................................................................... 31 5.4.3 Reset for Intel(R) LXT972M Transceiver................................................... 31 5.4.4 Hardware Configuration Settings ...........................................................33 Establishing Link .................................................................................................34 5.5.1 Auto-Negotiation.....................................................................................34 5.5.2 Parallel Detection ................................................................................... 35 MII Operation....................................................................................................... 36 5.6.1 MII Clocks............................................................................................... 37 5.6.2 Transmit Enable .....................................................................................38 5.6.3 Receive Data Valid ................................................................................. 38 5.6.4 Carrier Sense ......................................................................................... 39 5.6.5 Error Signals........................................................................................... 39 5.6.6 Collision .................................................................................................. 39 5.6.7 Loopback................................................................................................ 40 100 Mbps Operation ............................................................................................41 5.7.1 100BASE-X Network Operations ...........................................................41 5.7.2 Collision Indication ................................................................................. 44 5.7.3 100BASE-X Protocol Sublayer Operations ............................................ 45 10 Mbps Operation.............................................................................................. 50 5.8.1 10BASE-T Preamble Handling ............................................................... 50 5.8.2 10BASE-T Carrier Sense .......................................................................50 5.8.3 10BASE-T Dribble Bits ........................................................................... 50 5.8.4 10BASE-T Link Integrity Test ................................................................. 51 5.8.5 Link Failure ............................................................................................. 51 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 3 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.9 5.10 5.8.6 10BASE-T SQE (Heartbeat) .................................................................. 51 5.8.7 10BASE-T Jabber .................................................................................. 51 5.8.8 10BASE-T Polarity Correction................................................................ 51 Monitoring Operations ......................................................................................... 52 5.9.1 Monitoring Auto-Negotiation................................................................... 52 5.9.2 Monitoring Next Page Exchange............................................................ 52 5.9.3 LED Functions........................................................................................ 53 5.9.4 LED Pulse Stretching ............................................................................. 54 Boundary Scan (JTAG 1149.1) Functions .......................................................... 55 5.10.1 Boundary Scan Interface........................................................................ 55 5.10.2 State Machine ........................................................................................ 55 5.10.3 Instruction Register ................................................................................ 55 5.10.4 Boundary Scan Register ........................................................................ 56 5.10.5 Device ID Register ................................................................................. 56 6.0 Application Information..................................................................................................... 57 6.1 6.2 Magnetics Information ......................................................................................... 57 Typical Twisted-Pair Interface ............................................................................. 57 7.0 Electrical Specifications ................................................................................................... 61 7.1 7.2 Electrical Parameters .......................................................................................... 61 Timing Diagrams ................................................................................................. 65 8.0 9.0 10.0 Register Definitions - IEEE Base Registers ..................................................................... 75 Register Definitions - Product-Specific Registers ............................................................ 83 Intel(R) LXT972M Transceiver Package Specifications...................................................... 90 10.1 Top Label Markings............................................................................................. 91 11.0 Product Ordering Information ........................................................................................... 92 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Intel(R) LXT972M Transceiver Block Diagram....................................................... 11 Pin Assignments for Intel(R) LXT972M Transceiver 48-Pin LQFP Package ......... 12 Management Interface Read Frame Structure ................................................... 27 Management Interface Write Frame Structure ................................................... 27 Initialization Sequence for Intel(R) LXT972M Transceiver ..................................... 30 Link Establishment Overview) ............................................................................. 34 Clocking for 10BASE-T ...................................................................................... 37 Clocking for 100BASE-X .................................................................................... 37 Clocking for Link Down Clock Transition ............................................................ 38 Intel(R) LXT972M Transceiver Loopback Paths .................................................... 40 100BASE-X Frame Format ................................................................................ 41 100BASE-TX Data Path ..................................................................................... 42 100BASE-TX Reception with No Errors ............................................................. 43 100BASE-TX Reception with Invalid Symbol ..................................................... 43 100BASE-TX Transmission with No Errors ........................................................ 44 4 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 100BASE-TX Transmission with Collision .......................................................... 44 Intel(R) LXT972M Protocol Sublayers.................................................................... 45 LED Pulse Stretching ......................................................................................... 54 Intel(R) LXT972M Transceiver Typical Twisted-Pair Interface - Switch ................. 58 Intel(R) LXT972M Transceiver Typical Twisted-Pair Interface - NIC .....................59 Intel(R) LXT972M Transceiver Typical Media Independent Interface .................... 60 Intel(R) LXT972M Transceiver 100BASE-TX Receive Timing ............................... 65 Intel(R) LXT972M Transceiver 100BASE-TX Transmit Timing .............................. 66 Intel(R) LXT972M Transceiver 10BASE-T Receive Timing ................................... 67 Intel(R) LXT972M Transceiver 10BASE-T Transmit Timing .................................. 68 Intel(R) LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing ............... 69 Intel(R) LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing...................... 70 Intel(R) LXT972M Transceiver Auto-Negotiation and Fast Link Pulse Timing .......71 Intel(R) LXT972M Transceiver Fast Link Pulse Timing .......................................... 71 Intel(R) LXT972M Transceiver MDIO Input Timing ................................................ 72 Intel(R) LXT972M Transceiver MDIO Output Timing .............................................72 Intel(R) LXT972M Transceiver Power-Up Timing .................................................. 73 Intel(R) LXT972M Transceiver RESET_L Pulse Width and Recovery Timing .......74 PHY Identifier Bit Mapping ................................................................................. 78 Intel(R) LXT972M Transceiver LQFP Package Specifications............................... 90 Sample LQFP Package - Intel(R) LXT972M Transceiver ...................................... 91 Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel(R) LX972M Transceiver 91 Order Matrix for Intel(R) LXT972M Transceiver ..................................................... 92 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Related Documents from Intel............................................................................. 10 Intel(R) LXT972M Transceiver Signal Types ......................................................... 13 Intel(R) LXT972M Transceiver LQFP Numeric Pin List.......................................... 13 Intel(R) LXT972M Transceiver MII Data Interface Signal Descriptions.................. 16 Intel(R) LXT972M Transceiver MII Controller Interface Signal Descriptions .......... 17 Intel(R) LXT972M Transceiver Network Interface Signal Descriptions .................. 17 Intel(R) LXT972M Transceiver Standard Bus and Interface Signal Descriptions... 17 Intel(R) LXT972M Transceiver Configuration and LED Driver Signal Descriptions 18 Intel(R) LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions . 19 Intel(R) LXT972M Transceiver JTAG Test Signal Descriptions ............................. 19 Intel(R) LXT972M Transceiver Pin Types and Modes ........................................... 20 Intel(R) LXT972M Transceiver - PHY Device Address Selections......................... 26 Hardware Configuration Settings for Intel(R) LXT972M Transceiver .....................33 Carrier Sense, Loopback, and Collision Conditions ............................................ 39 4B/5B Coding ...................................................................................................... 46 Valid JTAG Instructions....................................................................................... 55 BSR Mode of Operation ...................................................................................... 56 Device ID Register for Intel(R) LXT972M Transceiver ........................................... 56 Magnetics Requirements.....................................................................................57 I/O Pin Comparison of NIC and Switch RJ-45 Setups ........................................57 Absolute Maximum Ratings for Intel(R) LXT972M Transceiver ............................. 61 Recommended Operating Conditions for Intel(R) LXT972M Transceiver ..............61 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 5 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) .............. 62 Digital I/O Characteristics1 - MII Pins .................................................................. 62 I/O Characteristics - REFCLK/XI and XO Pins.................................................... 63 I/O Characteristics - LED/CFG Pins .................................................................... 63 100BASE-TX Transceiver Characteristics .......................................................... 64 10BASE-T Transceiver Characteristics............................................................... 64 10BASE-T Link Integrity Timing Characteristics ................................................. 64 Intel(R) LXT972M Transceiver 100BASE-TX Receive Timing Parameters ........... 65 Intel(R) LXT972M Transceiver 100BASE-TX Transmit Timing Parameters ......... 66 Intel(R) LXT972M Transceiver 10BASE-T Receive Timing ................................... 67 Intel(R) LXT972M Transceiver 10BASE-T Transmit Timing .................................. 68 Intel(R) LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing............... 69 Intel(R) LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing ..................... 70 Intel(R) LXT972M Transceiver Auto-Negotiation / Fast Link Pulse Timing ............ 71 Intel(R) LXT972M Transceiver MDIO Timing ......................................................... 72 Intel(R) LXT972M Transceiver Power-Up Timing .................................................. 73 Intel(R) LXT972M Transceiver RESET_L Pulse Width and Recovery Timing ....... 74 Register Set for IEEE Base Registers................................................................. 75 Control Register - Address 0, Hex 0 ................................................................... 76 MII Status Register #1 - Address 1, Hex 1 .......................................................... 77 PHY Identification Register 1 - Address 2, Hex 2 ............................................... 78 PHY Identification Register 2 - Address 3, Hex 3 ............................................... 78 Auto-Negotiation Advertisement Register - Address 4, Hex 4 ............................ 79 Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5... 80 Auto-Negotiation Expansion - Address 6, Hex 6 ................................................. 81 Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 ................... 82 Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 82 Register Set for Product-Specific Registers ........................................................ 83 Configuration Register - Address 16, Hex 10...................................................... 84 Status Register #2 - Address 17, Hex 11 ............................................................ 85 Status Change Register - Address 19, Hex 13 ................................................... 86 LED Configuration Register - Address 20, Hex 14.............................................. 87 Digital Configuration Register - Address 26, Hex 1A .......................................... 88 Transmit Control Register - Address 30, Hex 1E ................................................ 89 Product Ordering Information .............................................................................. 92 6 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Revision History Intel(R) LXT972M Transceiver Datasheet Revision 005 Revision Date: 27-Oct-2005 Page 91 92 92 Description Added Figure 36 "Sample LQFP Package - Intel(R) LXT972M Transceiver" and Figure 37 "Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel(R) LX972M Transceiver" under Section 10.1, "Top Label Markings". Modified Table 57 "Product Ordering Information": added RoHS information Modified Figure 38 "Order Matrix for Intel(R) LXT972M Transceiver". Intel(R) LXT972M Transceiver Datasheet Revision 004 Revision Date: February 18, 2005 Page 10 92 Description Removed "Preliminary" label from document. Added Table 1 "Related Documents from Intel" Change to product ordering information in Chapter 11.0, "Product Ordering Information". Intel(R) LXT972M Transceiver Datasheet Revision 003 Revision Date: October 21, 2004 Page 1 11 Block diagram changed. Chapter 2.0, "Block Diagram for Intel(R) LXT972M Transceiver". Block diagram changed. Chapter 3.0, "Pin Assignments for Intel(R) LXT972M Transceiver". - Figure 2 "Pin Assignments for Intel(R) LXT972M Transceiver 48-Pin LQFP Package" changed. 12 - Figure 11 "Pin Assignments for Intel(R) LXT972M Transceiver Pb-Free 48-Pin LQFP". Added new figure for lead-free package. - Table 2 "Intel(R) LXT972M Transceiver Signal Types". Changed old Table 2 to Table 1 and table text changed. - Table 3 "Intel(R) LXT972M Transceiver LQFP Numeric Pin List" changed. Chapter 4.0, "Signal Descriptions for Intel(R) LXT972M Transceiver". 15 - Table 6 "Intel(R) LXT972M Transceiver Network Interface Signal Descriptions" changed. - Table 8 "Intel(R) LXT972M Transceiver Configuration and LED Driver Signal Descriptions" changed. Section 5.4.4, "Hardware Configuration Settings". 33 35 53 - Text changed. - Table 13 "Hardware Configuration Settings for Intel(R) LXT972M Transceiver" changed. Section 5.5.1.3, "Controlling Auto-Negotiation". Added text. Section 5.9.3, "LED Functions". Text changed. Chapter 7.0, "Electrical Specifications". 61 - Table 20 "Absolute Maximum Ratings for Intel(R) LXT972M Transceiver" changed. - Table 23 "Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins)" changed. - Table 27 "100BASE-TX Transceiver Characteristics" changed. 66 Section 7.2, "Timing Diagrams". Added timing diagrams. Description Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 7 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Intel(R) LXT972M Transceiver Datasheet Revision 003 Revision Date: October 21, 2004 Page Description Chapter 8.0, "Register Definitions - IEEE Base Registers" 75 - Table 40 "Register Set for IEEE Base Registers" changed. - Table 41 "Control Register - Address 0, Hex 0" changed. Chapter 9.0, "Register Definitions - Product-Specific Registers". 83 - Table 50 "Register Set for Product-Specific Registers" changed. - Table 54 "LED Configuration Register - Address 20, Hex 14" changed. - Table 56 "Transmit Control Register - Address 30, Hex 1E" 90 Chapter 10.0, "Intel(R) LXT972M Transceiver Package Specifications". - Figure 35 "Intel(R) LXT972M Transceiver LQFP Package Specifications" changed. Intel(R) LXT972M Transceiver Datasheet Revision 002 Revision Date: July 14, 2004 Page 1 10 21 22 23 26 30 33 36 37 45 47 47 47 48 53 80 80 85 Text changed. Figure 1 "Intel(R) LXT972M Transceiver Block Diagram" - Deleted ECL Driver from figure. Section 5.1, "Introduction" - Text changed. Section 5.2.1.1, "Twisted-Pair Interface" - Added text on MDI crossover. Section 5.2.1.2, "Fault Detection and Reporting" - Text changed. Section 5.3.2.1, "External Crystal/Oscillator" - Text changed. Table 12 "Hardware Configuration Settings for Intel(R) LXT972M Transceiver" - Bit value for 0.8 changed. Section 5.5.2, "Parallel Detection" - Text changed. Section 5.6.2, "Transmit Enable" - Text changed. Section 5.6.4, "Carrier Sense" - Text changed. Section 5.7.3.1.1, "Preamble Handling" - Text changed. Section 5.7.3.2.1, "Link" - Added text. Section 5.7.3.2.2, "Link Failure Override" - Added text. Section 5.7.3.2.4, "Receive Data Valid" - Text changed. Section 5.7.3.3.2, "Polarity Correction" - Text changed. Section 5.9.4, "LED Pulse Stretching" - Text changed. Table 46 "Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7" - Bits 7.10:0 and 7.13 changed. Table 47 "Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8" - Bits 8.18 and 8.10:0 changed. Table 52 "LED Configuration Register - Address 20, Hex 14" - Bit 20.0 changed. Description Intel(R) LXT972M Transceiver Datasheet Revision 001 Revision Date: July 2, 2004 Page Initial release of this document. Description 8 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 9 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 1.0 Introduction to This Document This document includes information on the Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver (called hereafter the LXT972M Transceiver) 1.1 Document Overview This document includes the following subjects: * * * * * * * * * * Chapter 2.0, "Block Diagram for Intel(R) LXT972M Transceiver" Chapter 3.0, "Pin Assignments for Intel(R) LXT972M Transceiver" Chapter 4.0, "Signal Descriptions for Intel(R) LXT972M Transceiver" Chapter 5.0, "Functional Description" Chapter 6.0, "Application Information" Chapter 7.0, "Electrical Specifications" Chapter 8.0, "Register Definitions - IEEE Base Registers" Chapter 9.0, "Register Definitions - Product-Specific Registers" Chapter 10.0, "Intel(R) LXT972M Transceiver Package Specifications" Chapter 11.0, "Product Ordering Information" 1.2 Table 1. Related Documents Related Documents from Intel Document Title Intel(R) LXT971A , LXT972A , LXT972M Single-Port 10/100 Mbps PHY Transceivers Specification Update Intel(R) LXT971A, LXT972A, and LXT972M 3.3V PHY Transceivers Design and Layout Guide - Application Note Magnetic Manufacturers for Networking Product Applications Application Note Document Number 249354 249016 248991 10 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 2.0 Block Diagram for Intel(R) LXT972M Transceiver Figure 1 is a block diagram of the LXT972M Transceiver. (This block diagram is the same as the block diagram on the first page of this document. This copy of the block diagram appears here as a convenience to the reader.) Figure 1. Intel(R) LXT972M Transceiver Block Diagram RESET_L ADDR[1:0] MDIO MDC Management / Mode Select Logic Power Supply Register Set Clock Generator VCC GND REFCLK/XI XO TX_EN TXD[3:0] TX PC S Manchester 10 Encoder Parallel/Serial Converter Scrambler 100 & Encoder Auto Negotiation Register Set OSP Pulse Shaper + TP Driver TP Out TPOP TPON - TX_CLK LED/CFG[3:1] JTAG 5 COL Collision Detect Clock Generator Media Select OSP Adaptive EQ with Baseline Wander Cancellation 100TX TDI TDO TMS TCK TRST_L + TP In TPIP TPIN RX_CLK RXD[3:0] R X PC S RX_DV CRS RX_ER Carrier Sense Data Valid Error Detect Serial-toParallel Converter 10 100 Manchester Decoder Decoder & Descrambler OSP Slicer 10BT + B3387-13 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 11 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 3.0 Pin Assignments for Intel(R) LXT972M Transceiver Figure 2 shows the pin assignments for the LXT972M Transceiver LQFP package. Figure 2. Pin Assignments for Intel(R) LXT972M Transceiver 48-Pin LQFP Package LED/CFG1 LED/CFG2 27 LED/CFG3 26 VCCIO RXD1 RXD2 RXD3 MDIO GND 36 35 34 33 32 31 30 29 28 NC NC VCCD RX_CLK RX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL 25 GND MDC NC 37 38 39 40 41 42 43 44 45 46 47 48 Revision Number 24 23 22 21 20 19 18 17 16 15 14 13 GND TRST_L TCK TMS TDO TDI TPIN TPIP VCCA TPON TPOP GNDA DJ972M A4 XXXXXXXX M C 'Y Y Part Number FPO Number Year ADDR0 10 ADDR1 11 REFCLK/X1 2 RESET_L 4 VCCIO 6 Pin 1 RBIAS 12 CRS 1 X0 3 GND 5 NC 7 NC 8 GND 9 B3814-02 12 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Note: Table 2. For the tables in this section and the following sections, the abbreviations listed in Table 2 are used for the "Type" column. Intel(R) LXT972M Transceiver Signal Types Abbreviation AI AO I I/O O OD Analog Input Analog Output Input Input/Output Output Open Drain Meaning Table 3 lists the LXT972M Transceiver LQFP pin numbers, symbols, and pin types. Table 3. Intel(R) LXT972M Transceiver LQFP Numeric Pin List (Sheet 1 of 2) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CRS REFCLK/XI XO RESET_L GND VCCIO NC NC GND ADDR0 ADDR1 RBIAS GNDA TPOP TPON VCCA TPIP TPIN TDI TDO TMS TCK TRST_L GND GND Symbol Type O AI AO I - - - - - I I AI - AO AO - AI AI I O I I I - - Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 13 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 3. Intel(R) LXT972M Transceiver LQFP Numeric Pin List (Sheet 2 of 2) Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol LED/CFG3 LED/CFG2 LED/CFG1 VCCIO GND MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV GND VCCD RX_CLK RX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL Type I/O I/O I/O - - I/O I O O O O O - - O O O I I I I I O 14 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 4.0 Signal Descriptions for Intel(R) LXT972M Transceiver Intel recommends the following configurations for unused pins: * Unused inputs. Configure all unused inputs and unused multi-function pins for inactive states. * Unused outputs. Leave all unused outputs floating. * No connects. Do not use pins designated as NC (no connect), and do not terminate them. Note: For the tables in this section, the abbreviations listed in Table 2, "Intel(R) LXT972M Transceiver Signal Types" on page 13 are used for the "Type" column. Tables in this section include the following * * * * * * * * Table 4, "Intel(R) LXT972M Transceiver MII Data Interface Signal Descriptions" Table 5, "Intel(R) LXT972M Transceiver MII Controller Interface Signal Descriptions" Table 6, "Intel(R) LXT972M Transceiver Network Interface Signal Descriptions" Table 7, "Intel(R) LXT972M Transceiver Standard Bus and Interface Signal Descriptions" Table 8, "Intel(R) LXT972M Transceiver Configuration and LED Driver Signal Descriptions" Table 9, "Intel(R) LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions" Table 10, "Intel(R) LXT972M Transceiver JTAG Test Signal Descriptions" Table 11, "Intel(R) LXT972M Transceiver Pin Types and Modes" Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 15 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 4 lists signal descriptions of the LXT972M Transceiver MII data interface pins. Table 4. Intel(R) LXT972M Transceiver MII Data Interface Signal Descriptions LQFP Pin# 47 46 45 44 43 Symbol TXD3 TXD2 TXD1 TXD0 TX_EN I I Type Transmit Data. TXD is a group of parallel data signals that are driven by the MAC. TXD[3:0] transition synchronously with respect to TX_CLK. TXD[0] is the least-significant bit. Transmit Enable. The MAC asserts this signal when it drives valid data on TXD. This signal must be synchronized to TX_CLK. Transmit Clock. 42 TX_CLK O TX_CLK is sourced by the PHY in both 10 and 100 Mbps operations. 2.5 MHz for 10 Mbps operation 25 MHz for 100 Mbps operation. 33 34 35 36 RXD3 RXD2 RXD1 RXD0 O Receive Data. RXD is a group of parallel signals that transition synchronously with respect to RX_CLK. RXD[0] is the least-significant bit. Receive Data Valid. 37 RX_DV O The LXT972M Transceiver asserts this signal when it drives valid data on RXD. This output is synchronous to RX_CLK. Receive Error. 41 RX_ER O Signals a receive error condition has occurred. This output is synchronous to RX_CLK. Receive Clock. 25 MHz for 100 Mbps operation. 40 RX_CLK O 2.5 MHz for 10 Mbps operation. For details, see "Clock Requirements" on page 28 in Chapter 5.0, "Functional Description". Collision Detected. 48 COL O The LXT972M Transceiver asserts this output when a collision is detected. This output remains High for the duration of the collision. This signal is asynchronous and is inactive during full- duplex operation. Carrier Sense. During half-duplex operation (Register bit 0.8 = 0), the LXT972M Transceiver asserts this output when either transmitting or receiving data packets. During full-duplex operation (Register bit 0.8 = 1), CRS is asserted only during receive. CRS assertion is asynchronous with respect to RX_CLK. CRS is de-asserted on loss of carrier, synchronous to RX_CLK. Signal Description 1 CRS O 16 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 5 lists signal descriptions of the LXT972M Transceiver MII controller interface pins. Table 5. Intel(R) LXT972M Transceiver MII Controller Interface Signal Descriptions LQFP Pin# Symbol Type Signal Description Management Data Clock. 32 MDC I Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. 31 MDIO I/O Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. Table 6 lists signal descriptions of the LXT972M Transceiver network interface pins. Table 6. Intel(R) LXT972M Transceiver Network Interface Signal Descriptions LQFP Pin# 14 15 17 18 Symbol TPOP TPON TPIP TPIN Type Signal Description Twisted-Pair Outputs, Positive and Negative. AO During 100BASE-TX or 10BASE-T operation, TPOP/N pins drive IEEE 802.3 compliant pulses onto the line. Twisted-Pair Inputs, Positive and Negative. AI During 100BASE-TX or 10BASE-T operation, TPIP/N pins receive differential 100BASE-TX or 10BASE-T signals from the line. Table 7 lists signal descriptions of the LXT972M Transceiver standard bus and interface signals. Table 7. Intel(R) LXT972M Transceiver Standard Bus and Interface Signal Descriptions LQFP Pin# 10 11 Symbol ADDR0 ADDR1 Type Address. Set device address. Signal Description I Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 17 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 8 lists signal descriptions of the LXT972M Transceiver configuration and LED driver pins. Note: Table 8. Pull-up/pull-down resistors of 10k Ohms can be implemented if LEDs are not used in the design. Intel(R) LXT972M Transceiver Configuration and LED Driver Signal Descriptions LQFP Pin# Symbol Type Reset. 4 RESET_L I This active Low input is ORed with the control register Reset bit (Register bit 0.15). The LXT972M Transceiver reset cycle is extended to 258 s (nominal) after reset is de-asserted. Reference Current Bias. 12 RBIAS AI This pin provides bias current for the internal circuitry. Must be tied to ground through a 22.1 k, 1% resistor. Reference Clock Input / Crystal Input and Crystal Output. 2 3 REFCLK/XI XO AI and AO A 25 MHz crystal oscillator circuit can be connected across XI and XO. A clock can also be used at XI. Refer to Section 5.3.2, "Clock Requirements" on page 28 in the Functional Description section. LED Drivers 1-3. These pins drive LED indicators. Each LED can display one of several available status conditions as selected by the LED Configuration Register. (For details, see Table 54, "LED Configuration Register - Address 20, Hex 14" on page 87.) Configuration Inputs 1-3. These pins also provide initial configuration settings. (For details, see Table 13, "Hardware Configuration Settings for Intel(R) LXT972M Transceiver" on page 33.) Signal Description 26 27 28 LED/CFG3 LED/CFG2 LEDCFG1 I/O 18 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 9 lists signal descriptions of the LXT972M Transceiver power, ground, and no-connect pins. Table 9. Intel(R) LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions LQFP Pin# 13 5, 9, 24, 25, 30, 38 Symbol GNDA GND Type - - Analog Ground. Ground Input/Output. Ground return for digital I/O circuits (VCCIO). MII Power. 6, 29 VCCIO - Requires either a 3.3 V or a 2.5 V supply. Must be supplied from the same source used to power the MAC on the other side of the MII. For the LXT972M Transceiver, VCCIO is 3.3 V. 16 39 7, 8 VCCA VCCD NC - - - Analog Power. Requires a 3.3 V power supply. Digital Power. Requires a 3.3 V power supply. No Connection. These pins are not used and must not be terminated. Signal Description Table 10 lists signal descriptions of LXT972M Transceiver Joint Test Action Group (JTAG) pins. Note: If a JTAG port is not used, these pins do not need to be terminated. Table 10. Intel(R) LXT972M Transceiver JTAG Test Signal Descriptions LQFP Pin# 19 20 21 22 23 Symbol Type Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Clock input for boundary scan. Test Reset. This active-low test reset input is sourced by ATE. Signal Description TDI TDO TMS TCK TRST_L I O I I I Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 19 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 11 lists pin types and modes of the LXT972M Transceiver. Note: * * * * DH = Driven High (Logic 1) DL = Driven Low (Logic 0) HZ = High Impedance ID = Internal Pull-Down (Weak) Table 11. Intel(R) LXT972M Transceiver Pin Types and Modes Modes HWReset SFTPWRDN ISOLATE RXD3:0 DL DL HZ with ID RX_DV DL DL HZ with ID Tx/Rx CLKS Output DH Active HZ with ID RX_ER Output DL DL HZ with ID COL Output DL DL HZ with ID CRS Output DL DL HZ with ID TXD3:0 Input ID ID ID TX_EN Input ID ID ID 20 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.0 Functional Description This chapter has the following sections: * * * * * * * * * * Section 5.1, "Device Overview" Section 5.2, "Network Media / Protocol Support" Section 5.3, "Operating Requirements" Section 5.4, "Initialization" Section 5.5, "Establishing Link" Section 5.6, "MII Operation" Section 5.7, "100 Mbps Operation" Section 5.8, "10 Mbps Operation" Section 5.9, "Monitoring Operations" Section 5.10, "Boundary Scan (JTAG 1149.1) Functions" Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 21 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.1 Device Overview The LXT972M Transceiver is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly drives either a 100BASE-TX line or a 10BASE-T line. 5.1.1 Comprehensive Functionality The LXT972M Transceiver provides a standard Media Independent Interface (MII) for 10/100 MACs. The LXT972M Transceiver performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. It also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. If the LXT972M Transceiver is not set for forced operation, it uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT972M Transceiver auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT972M Transceiver automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and sets its operating conditions accordingly. The LXT972M Transceiver provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps. 5.1.2 Optimal Signal Processing Architecture The LXT972M Transceiver incorporates high-efficiency Optimal Signal Processing (OSP) design techniques, which combine optimal properties of digital and analog signal processing. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results in improved receiver noise and cross-talk performance. The OSP signal processing scheme also requires substantially less computational logic than traditional DSP-based designs. This lowers power consumption and also reduces the logic switching noise generated by DSP engines. This logic switching noise can be a considerable source of EMI generated on the device's power supplies. The OSP-based LXT972M Transceiver provides improved data recovery, EMI performance, and low power consumption. 22 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.2 Network Media / Protocol Support This section includes the following: * Section 5.2.1, "10/100 Network Interface" * Section 5.2.2, "MII Data Interface" * Section 5.2.3, "Configuration Management Interface" The LXT972M Transceiver supports both 10BASE-T and 100BASE-TX Ethernet over twistedpair. 5.2.1 10/100 Network Interface The network interface port consists of two differential signal pairs. For specific pin assignments, see Chapter 4.0, "Signal Descriptions for Intel(R) LXT972M Transceiver". The LXT972M Transceiver output drivers can generate one of the following outputs: * 100BASE-TX * 10BASE-T When not transmitting data, the LXT972M Transceiver generates IEEE 802.3-compliant link pulses or idle code. Depending on the mode selected, input signals are decoded as one of the following: When not transmitting data, the LXT972M Transceiver generates IEEE 802.3-compliant link pulses or idle code. Depending on the mode selected, input signals are decoded as one of the following: * 100BASE-TX * 10BASE-T Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 23 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.2.1.1 Twisted-Pair Interface The LXT972M Transceiver supports either 100BASE-TX or 10BASE-T connections over 100 , Category 5, Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT972M Transceiver continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT972M Transceiver generates "IDLE" symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link up. Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT972M Transceiver has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings allow the designer to match the output waveform to the magnetic characteristics. On the receive side, the internal impedance is high enough that it has no practical effect on the external termination circuit. (For the slew rate settings, see Table 56, "Transmit Control Register - Address 30, Hex 1E" on page 89.) Note: On the LXT972M Transceiver, MDIX crossover (MDIX) is supported by board design. 5.2.1.2 Remote Fault Detection and Reporting The LXT972M Transceiver supports the remote fault detection and reporting mechanisms. "Remote Fault" refers to a MAC-to-MAC communication function that is transparent to PHY layer devices. It is used only during auto-negotiation, and is applicable only to twisted-pair links. Remote Fault Detection. Register bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the link partner that the link is down because the advertising device detected a local fault. When the LXT972M Transceiver receives a Remote Fault indication from its partner during autonegotiation, the following occurs: * Register bit 5.13 in the Link Partner Base Page Ability Register is set. * Remote Fault Register bit 1.4 in the MII Status Register is set to pass this information to the local controller. 24 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.2.2 MII Data Interface The LXT972M Transceiver supports a standard Media Independent Interface (MII). The MII consists of a data interface and a management interface. The MII Data Interface passes data between the LXT972M Transceiver and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically, once the operating conditions of the network link have been determined. For details, see Section 5.6, "MII Operation" on page 36. Increased MII Drive Strength. A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or through a connector. The MII drive strength in the LXT972M Transceiver can be increased by setting Register bit 26.11 through software control. Setting Register bit 26.11 = 1 through the MDC/MDIO interface sets the MII pins (RXD[3:0], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive strength. 5.2.3 Configuration Management Interface The LXT972M Transceiver provides both an MDIO interface and a reduced hardware control interface for device configuration and management. 5.2.3.1 MDIO Management Interface MDIO management interface topics include the following: * Section 5.2.3.1.1, "MDIO Addressing for Intel(R) LXT972M Transceiver" * Section 5.2.3.1.2, "MDIO Frame Structure" The LXT972M Transceiver supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT972M Transceiver. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 standard. The LXT972M Transceiver also supports additional registers for expanded functionality. The LXT972M Transceiver supports multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using an "X.Y" notation, where X is the register number (0-31) and Y is the bit number (0-15). 5.2.3.1.1 MDIO Addressing for Intel(R) LXT972M Transceiver The MDIO addressing protocol allows a controller to communicate with multiple LXT972M Transceivers.As listed in Table 12, pins ADDR[1:0] determine the PHY device address that is selected. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 25 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 12. Intel(R) LXT972M Transceiver - PHY Device Address Selections ADDR1 (Pin 11) 0 0 1 1 ADDR0 (Pin 10) 0 1 0 1 PHY Device Address Selected 0 1 28 29 26 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.2.3.1.2 MDIO Frame Structure The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is shown in Figure 3 and Figure 4 (Read and Write). MDIO Interface timing is given in Chapter 7.0, "Electrical Specifications". Figure 3. Management Interface Read Frame Structure MDC MDIO (Read) High Z 32 "1"s Preamble 0 ST 1 1 0 Op Code A4 A3 PHY Address A0 R4 R3 Register Address R0 Z 0 D15 D15D14 D14 D1 Data Read D1 D0 Idle Turn Around Write B3489-01 Figure 4. Management Interface Write Frame Structure MDC MDIO (Write) Idle 32 "1"s Preamble 0 ST 1 0 1 Op Code A4 A3 PHY Address A0 R4 R3 Register Address R0 1 0 Turn Around D15 D14 Data D1 D0 Idle Write B3490-01 5.2.3.2 Hardware Control Interface The LXT972M Transceiver provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the hardware configuration pins to set device configuration. For details, see Section 5.4.4, "Hardware Configuration Settings" on page 33. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 27 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.3 5.3.1 Operating Requirements Power Requirements The LXT972M Transceiver requires three power supply inputs: * VCCA * VCCD * VCCIO The digital and analog circuits require 3.3 V supplies (VCCA and VCCD). These inputs may be supplied from a single source. Each supply input must be de-coupled to ground. An additional supply may be used for the MII (VCCIO). The supply may be either +2.5 V or +3.3 V. Also, the inputs on the MII interface are tolerant to 5 V signals from the controller on the other side of the MII interface. For MII I/O characteristics, see Table 24, "Digital I/O Characteristics1 - MII Pins" on page 62. Note: Note: Bring up power supplies as close to the same time as possible. As a matter of good practice, keep power supplies as clean as possible. 5.3.2 5.3.2.1 Clock Requirements External Crystal/Oscillator The LXT972M Transceiver requires a reference clock input that is used to generate transmit signals and recover receive signals. It may be provided by either of two methods: by connecting a crystal across the oscillator pins (XI and XO) with load capacitors, or by connecting an external clock source to pin XI. The connection of a clock source to the XI pin requires the XO pin to be left open. To minimize transmit jitter, Intel recommends a crystal-based clock instead of a derived clock (that is, a PLLbased clock). A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications. For clock timing requirements, see Table 25, "I/O Characteristics - REFCLK/XI and XO Pins" on page 63. 5.3.2.2 MDIO Clock The MII management channel (MDIO) also requires an external clock. The managed data clock (MDC) speed is a maximum of 8 MHz. For details, see Table 37, "Intel(R) LXT972M Transceiver MDIO Timing" on page 72. 28 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.4 Initialization This section includes the following topics: * * * * Section 5.4.1, "MDIO Control Mode and Hardware Control Mode" Section 5.4.2, "Reduced-Power Modes" Section 5.4.3, "Reset for Intel(R) LXT972M Transceiver" Section 5.4.4, "Hardware Configuration Settings" When the LXT972M Transceiver is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 29 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 5 shows the initialization sequence for the LXT972M Transceiver. The configuration bits may be set by the Hardware Control or MDIO interface. Figure 5. Initialization Sequence for Intel(R) LXT972M Transceiver Power-up or Reset Read H/W Control Interface Initialize MDIO Registers Pass Control to MDIO Interface Software Reset? Yes Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset or Power-Up Reset B3502-02 30 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.4.1 MDIO Control Mode and Hardware Control Mode In the MDIO Control mode, the LXT972M Transceiver reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface. The following modes are available using MDIO Control. * Force network link operation to: -- 100BASE-TX, Full-Duplex -- 100BASE-TX, Half-Duplex -- 10BASE-T, Full-Duplex -- 10BASE-T, Half-Duplex * Allow auto-negotiation/parallel-detection On power-up or hardware reset, the LXT972M Transceiver reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using the Hardware Control: * Auto-negotiation-enabled advertising, either: -- 10/100 BASE-T Full/Half Duplex -- 10/100 BASE-T Half Duplex * LXT972M Transceiver device ID enable * Link Hold-off When the network link is forced to a specific configuration, the LXT972M Transceiver immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT972MTransceiver begins the auto-negotiation/parallel-detection operation. 5.4.2 Reduced-Power Modes This section discusses the LXT972M Transceiver reduced-power modes. 5.4.2.1 Software Power Down Software power-down control is provided by Register bit 0.11 in the Control Register. (See Table 41 on page 76.) During soft power-down, the following conditions are true: * The network port is shut down. * The MDIO registers remain accessible. 5.4.3 Reset for Intel(R) LXT972M Transceiver The LXT972M Transceiver provides both hardware and software resets, each of which manage differently the configuration control of auto-negotiation, speed, and duplex-mode selection. For a software reset, Register bit 0.15 = 1. For register bit definitions used for software reset, see Table 41, "Control Register - Address 0, Hex 0" on page 76. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 31 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver * During a software reset, bit settings in Table 45, "Auto-Negotiation Advertisement Register Address 4, Hex 4" on page 79 are not re-read from the LXT972M Transceiver configuration pins. Instead, the bit settings revert to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. * During a software reset, registers are available for reading. To see when the LXT972M Transceiver has completed reset, the reset bit can be polled (that is, Register bit 0.15 = 0). For pin settings used during a hardware reset, see Section 5.4.4, "Hardware Configuration Settings". During a hardware reset, configuration settings for auto-negotiation and speed are read in from pins, and register information is unavailable for 1 ms after de-assertion of the reset. 32 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.4.4 Hardware Configuration Settings The LXT972M Transceiver provides a hardware option to set the initial device configuration. As listed in Table 13, the hardware option uses the hardware configuration pins, the settings for which provide control bits. Table 13. Hardware Configuration Settings for Intel(R) LXT972M Transceiver LED/CFG Pin Settings1 Resulting Register Bit Values Control Register Auto-Negotiation Advertisement Register 100 BASE-TX FullDuplex 4.8 Half 10 Full Disabled Half 100 Full 100 Only Enabled 10/100 Half Full/Half Half Only Full or Half L H H H H H L L H H H L H L H 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 L H L L L H 0 1 0 0 1 L L L 0 0 N/A Auto-Negotiation Advertisement 100 BASE -TX 4.7 10 BASE-T FullDuplex 4.6 10 BASE-T Desired Mode AutoNeg. Speed (Mbps) Duplex 1 2 3 AutoNeg. 0.12 Speed 0.13 FullDuplex 0.8 4.5 1. L = Low, and H = High. For LED/CFG pin assignments, see Chapter 3.0, "Pin Assignments for Intel(R) LXT972M Transceiver". Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 33 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.5 Establishing Link Figure 6 shows an overview of link establishment for the LXT972M Transceiver. Note: When a link is established by parallel detection, the LXT972M Transceiver sets the duplex mode to half-duplex, as defined by the IEEE 802.3 standard. Figure 6. Link Establishment Overview) Power-Up, Reset, or Link Failure Start Disable Auto-Negotiation Enable Auto-Neg/Parallel Detection 0.12 = 0 Check Value 0.12 0.12 = 1 Go To Forced Settings Attempt AutoNegotiation Listen for 100TX Idle Symbols Listen for 10T Link Pulses YES Done Link Up? NO B3496-01 5.5.1 Auto-Negotiation If not configured for forced operation, the LXT972M Transceiver attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses spaced 62.5 s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be absent or present to indicate a `0' or a `1'. Each FLP burst exchanges 16 bits of data, which are referred to as a "link code word". All devices that support auto-negotiation must implement the "Base Page" defined by the IEEE 802.3 standard (Registers 4 and 5). The LXT972M Transceiver also supports the optional "Next Page" function as listed in Table 48, "Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7" on page 82 and Table 49, "Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8" on page 82. 5.5.1.1 Base Page Exchange By exchanging Base Pages, the LXT972M Transceiver and its link partner communicate their capabilities to each other. Both sides must receive at least three consecutive identical base pages for negotiation to continue. Each side identifies the highest common capabilities that both sides support, and each side configures itself accordingly. 34 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.5.1.2 Manual Next Page Exchange "Next Page Exchange" information is additional information that exceeds the information required by Base Page exchange and that is sent by "Next Pages". The LXT972M Transceiver fully supports the IEEE 802.3 standard method of negotiation through the Next Page exchange. The Next Page exchange uses Register 7 to send information and Register 8 to receive it. Next Page exchange occurs only if both ends of the link partners advertise their ability to exchange Next Pages. Register bit 6.1 is used to make manual next page exchange easier for software. This register bit is cleared when a new negotiation occurs, preventing the user from reading an old value in Register 6 and assuming there is valid information in Registers 5 and 8. 5.5.1.3 Controlling Auto-Negotiation When auto-negotiation is controlled by software, Intel recommends the following steps: 1. After power-up, power-down, or reset, the power-down recovery time (specified in Table 39, "Intel(R) LXT972M Transceiver RESET_L Pulse Width and Recovery Timing" on page 74) must be exhausted before proceeding. 2. Set the Auto-Negotiation Advertisement Register bits in Register 4 as desired. 3. Enable auto-negotiation. (Set MDIO Register bit 0.12 = 1.) 4. To ensure proper operation, enable or restart auto-negotiation as soon as possible after writing to Register 4. 5.5.2 Parallel Detection In parallel with auto-negotiation, the LXT972M Transceiver also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device automatically reverts to the corresponding speed in half-duplex mode. Parallel detection allows the LXT972M Transceiver to communicate with devices that do not support auto-negotiation. When parallel detection resolves a link, the link must be established in half-duplex mode. According to IEEE standards, the forced link partner cannot be configured to full-duplex. If the auto-negotiation link partner does not advertise half-duplex capability at the speed of the forced link partner, link is not established. The IEEE Standard prevents full-duplex-to-half-duplex link connections. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 35 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.6 MII Operation This section includes the following topics: * * * * * * * Section 5.6.1, "MII Clocks" Section 5.6.2, "Transmit Enable" Section 5.6.3, "Receive Data Valid" Section 5.6.4, "Carrier Sense" Section 5.6.5, "Error Signals" Section 5.6.6, "Collision" Section 5.6.7, "Loopback" The LXT972M Transceiver implements the Media Independent Interface (MII) as defined by the IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT972M Transceiver (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. The following signals are used to pass received data to the MAC: * * * * * * COL CRS RX_CLK RX_DV RX_ER RXD[3:0] The following signals are used to transmit data from the MAC: * TX_CLK * TX_EN * TXD[3:0] The LXT972M Transceiver supplies both clock signals as well as separate outputs for carrier sense and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles. 36 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.6.1 MII Clocks The LXT972M Transceiver is the master clock source for data transmission, and it supplies both MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. * When the link is operating at 100 Mbps, the clocks are set to 25 MHz. * When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz. Figure 7 through Figure 9 show the clock cycles for each mode. Note: The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The LXT972M Transceiver samples these signals on the rising edge of TX_CLK. Figure 7. Clocking for 10BASE-T 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle TX_CLK 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle RX_CLK Constant 25 MHz XI B3390-01 Figure 8. Clocking for 100BASE-X 25 MHz once 100BASE-X Link Established 2.5 MHz during auto-negotiation TX_CLK 25 MHz once 100BASE-X Link Established 2.5 MHz during auto-negotiation RX_CLK Constant 25 MHz XI B3391-01 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 37 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 9. Clocking for Link Down Clock Transition Link-Down Condition/Auto-Negotiate Enabled RX_CLK TX_CLK Any Clock 2.5 MHz Clock Clock transition time does not exceed 2X the nominal clock period: 10 Mbps = 2.5 MHz 100 Mbps = 25 MHz B3503-01 5.6.2 Transmit Enable The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert TX_EN after the last nibble of the packet. 5.6.3 Receive Data Valid The LXT972M Transceiver asserts RX_DV when it receives a valid packet. Timing changes depend on line operating speed: * For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the data packet. * For 10BASE-T links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the Start of Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet. 38 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.6.4 Carrier Sense Carrier Sense (CRS) is an asynchronous output. * CRS is always generated when the LXT972M Transceiver receives a packet from the line. * CRS is also generated when the LXT972M Transceiver is in half-duplex mode when a packet is transmitted. Table 14 summarizes the conditions for assertion of carrier sense, data loopback, and collision signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode. Table 14. Carrier Sense, Loopback, and Collision Conditions Speed Duplex Condition Full-Duplex Half-Duplex Full-Duplex 10 Mbps Half-Duplex, Register bit 16.8 = 0 Half-Duplex, Register bit 16.8 = 1 Carrier Sense Receive Only Transmit or Receive Receive Only Transmit or Receive Transmit or Receive Test Loopback1, 2 Yes No Yes Yes No Operational Loopback1, 2 No No No Yes No None Transmit and Receive None Transmit and Receive Transmit and Receive Collision 100 Mbps 1. Test Loopback is enabled when Register bit 0.14 = 1. 2. For descriptions of Test Loopback and Operational Loopback, see Section 5.6.7, "Loopback" on page 40. 5.6.5 Error Signals When the LXT972M Transceiver is in 100 Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives "0101" on the RXD pins. The TX_ER function that forces `H' symbols out on the TPOP/TPON twisted pair is not implemented in the LXT972M Transceiver. 5.6.6 Collision The LXT972M Transceiver asserts its collision signal asynchronously to any clock whenever the line state is half-duplex and the transmitter and receiver are active at the same time. Table 14 summarizes the conditions for assertion of carrier sense, data loopback, and collision signals. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 39 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.6.7 Loopback The LXT972M Transceiver provides the following loopback functions: * Section 5.6.7.1, "Operational Loopback" * Section 5.6.7.2, "Internal Digital Loopback (Test Loopback)" Figure 10 shows LXT972M Transceiver loopback paths. Figure 10. Intel(R) LXT972M Transceiver Loopback Paths Intel(R) LXT972M Transceiver Operational Loopback Test Loopback MII 10T Loopback Digital Block 100X Loopback Analog Block TX Driver B3485-01 5.6.7.1 Operational Loopback * Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0. Data that the MAC (TXData) transmits loops back on the receive side of the MII (RXData). * Operational loopback is not provided for 100 Mbps links, full-duplex links, or when Register 16.8 = 1. 40 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.6.7.2 Internal Digital Loopback (Test Loopback) A test loopback function is provided for diagnostic testing of the LXT972M Transceiver. During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT972M Transceiver and returned to the MAC. Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by setting the following register bits: * Register bit 0.14 = 1 (Setting to enable loopback mode) * Register bit 0.8 = 1 (Setting for full-duplex mode) * Register bit 0.12 = 0. (Disable auto-negotiation.) 5.7 5.7.1 100 Mbps Operation 100BASE-X Network Operations During 100BASE-X operation, the LXT972M Transceiver transmits and receives 5-bit symbols across the network link. Figure 11 shows the structure of a standard frame packet in 100BASE-X mode. When the MAC is not actively transmitting data, the LXT972M Transceiver sends out Idle symbols on the line. As Figure 11 shows, the MAC starts each transmission with a preamble pattern. As soon as the LXT972M Transceiver detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD, symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the SFD, packet data, and CRC. Once the packet ends, the LXT972M Transceiver transmits the End-of-Stream Delimiter (ESD, symbols T and R) and then returns to transmitting Idle symbols. For details on the symbols used, see 4B/5B coding listed in Table 15, "4B/5B Coding" on page 46. Figure 11. 100BASE-X Frame Format 64-Bit Preamble (8 Octets) Destination and Source Address (6 Octets each) Packet Length (2 Octets) Data Field Frame Check Field InterFrame Gap / Idle Code (Pad to minimum packet size) (4 Octets) (> 12 Octets) P0 P1 P6 SFD DA DA SA SA L1 L2 D0 D1 Dn CRC I0 IFG Replaced by /J/K/ code-groups Start-of-Stream Delimiter (SSD) Start-of-Frame Delimiter (SFD) Replaced by /T/R/ code-groups End-of-Stream Delimiter (ESD) B3466-01 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 41 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver As shown in Figure 12, in 100BASE-TX mode, the LXT972M Transceiver scrambles and transmits the data to the network using MLT-3 line code. MLT-3 signals received from the network are de-scrambled, decoded, and sent across the MII to the MAC. Figure 12. 100BASE-TX Data Path Standard Data Flow D0 D1 D2 D3 Parallel to Serial +1 0 0 -1 0 Scramble D0 D1 D2 D3 Serial to Parallel 4B/5B S0 S1 S2 S3 S4 DeScramble MLT3 Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1... Scrambler Bypass Data Flow S0 S1 S2 S3 S4 Serial to Parallel Parallel to Serial +1 0 0 -1 0 S0 S1 S2 S3 S4 MLT3 Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1... B3467-01 42 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 13 shows normal reception with no errors. Figure 13. 100BASE-TX Reception with No Errors RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA DA DA DA CRC CRC CRC CRC RX_ER B3468-01 As shown in Figure 14, when the LXT972M Transceiver receives invalid symbols from the line, it asserts RX_ER. Figure 14. 100BASE-TX Reception with Invalid Symbol RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA DA XX XX XX XX XX XX XX XX XX XX RX_ER B3469-01 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 43 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.7.2 Collision Indication Figure 15 shows normal transmission. Figure 15. 100BASE-TX Transmission with No Errors TX_CLK TX_EN TXD<3:0> CRS COL B3470-01 P R E A M B L E DA DA DA DA DA DA DA DA DA Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 16. Figure 16. 100BASE-TX Transmission with Collision TX_CLK TX_EN TXD<3:0> CRS COL B3471-01 P R E A M B L E JAM JAM JAM JAM 44 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.7.3 100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT972M Transceiver is a Physical Layer 1 (PHY) device. The LXT972M Transceiver implements the following sublayers of the reference model defined by the IEEE 802.3 standard, and discussed from the reference model point of view: * Section 5.7.3.1, "Physical Coding Sublayer" * Section 5.7.3.2, "Physical Medium Attachment Sublayer" * Section 5.7.3.3, "Twisted-Pair Physical Medium Dependent Sublayer" Figure 17 shows the LXT972M Transceiver protocol sublayers. Figure 17. Intel(R) LXT972M Protocol Sublayers MII Interface Intel(R) LXT972M Transceiver Encoder/Decoder Serializer/De-serializer PCS Sublayer PMA Sublayer Link/Carrier Detect PMD Sublayer Scrambler/ De-scrambler 100BASE-TX B3514-01 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 45 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.7.3.1 Physical Coding Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. 5.7.3.1.1 Preamble Handling When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-ofStream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues to encode the remaining MII data, following the 4B/5B coding in Table 15, until TX_EN is deasserted. It then returns to supplying IDLE symbols to the line driver. In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD. In 100 Mbps operation, preamble is always passed through the PCS layer to the MII interface. Table 15. 4B/5B Coding (Sheet 1 of 2) Code Type 4B Code 3210 0000 0001 0010 0011 0100 0101 0110 DATA 0111 1000 1001 1010 1011 1100 1101 1110 1111 IDLE undefined Name 0 1 2 3 4 5 6 7 8 9 A B C D E F I 1 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 1 1 1 11 Interpretation Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F Used as inter-stream fill code 1. The /I/ (Idle) code group is sent continuously between frames. 2. The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T/. 4. An /H/ (Error) code group is used to signal an error condition. 46 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 15. 4B/5B Coding (Sheet 2 of 2) Code Type 4B Code 3210 0101 0101 CONTROL Undefined Undefined Undefined Undefined Undefined Undefined Undefined INVALID Undefined Undefined Undefined Undefined Undefined Undefined 1. 2. 3. 4. T3 R3 H4 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Name J2 K2 5B Code 43210 11000 10001 Interpretation Start-of-Stream Delimiter (SSD), part 1 of 2 Start-of-Stream Delimiter (SSD), part 2 of 2 End-of-Stream Delimiter (ESD), part 1 of 2 End-of-Stream Delimiter (ESD), part 2 of 2 Transmit Error. Used to force signaling errors Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 47 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.7.3.2 Physical Medium Attachment Sublayer 5.7.3.2.1 Link In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive idle symbols in any 2 ms period. This operation filters out small noise hits that may disrupt the link. In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive idle symbols in any 2 ms period. This operation filters out small noise hits that may disrupt the link. For short periods, MLT-3 idle waveforms meet all criteria for 10BASE-T start delimiters. A working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms. However, the PHY does not bring up a permanent 10 Mbps link. The LXT972M Transceiver reports link failure through the MII status bits (Register bits 1.2 and 17.10). Link failure causes the LXT972M Transceiver to re-negotiate if auto-negotiation is enabled. 5.7.3.2.2 Link Failure Override The LXT972M Transceiver normally transmits data packets only if it detects the link is up. Setting Register bit 16.14 = 1 overrides this function, allowing the LXT972M Transceiver to transmit data packets even when the link is down. This feature is provided as a transmit diagnostic tool. Note: Auto-negotiation must be disabled to transmit data packets in the absence of link. If autonegotiation is enabled, the LXT972M Transceiver automatically transmits FLP bursts if the link is down. During normal operation, Intel does not recommend setting Register bit 16.14 for 100 Mbps receive functions because receive errors may be generated. Caution: 5.7.3.2.3 Carrier Sense For 100BASE-TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R. However, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted. Intel does not recommend using CRS for Interframe Gap (IFG) timing for the following reasons: * CRS de-assertion time is slightly longer than CRS assertion time. As a result, an IFG interval appears somewhat shorter to the MAC than it actually is on the wire. * CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in halfduplex mode. 5.7.3.2.4 Receive Data Valid The LXT972M Transceiver asserts RX_DV to indicate that the received data maps to valid symbols. In 100 Mbps operation, RX_DV is active with the first nibble of preamble. 48 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.7.3.3 Twisted-Pair Physical Medium Dependent Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides signal scrambling and descrambling functions, line coding and decoding functions (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), as well as receiving, polarity correction, and baseline wander correction functions. 5.7.3.3.1 Scrambler/Descrambler The purpose of the scrambler/descrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. Scrambler Seeding. Once the transmit data (or Idle symbols) are properly encoded, they are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed. Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the design. Scrambler Bypass. The scrambler/de-scrambler can be bypassed by setting Register bit 16.12 = 1. Scrambler bypass is provided for diagnostic and test support. 5.7.3.3.2 Polarity Correction The 100 Mbps twisted pair signaling is not polarity sensitive. As a result, the polarity status is not a valid status indicator. 5.7.3.3.3 Baseline Wander Correction The LXT972M Transceiver provides a baseline wander correction function for when the LXT972M Transceiver is under network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by definition "unbalanced". As a result, the average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are completely data dependent. The LXT972M Transceiver baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case packets over all cable lengths. 5.7.3.3.4 Programmable Slew Rate Control The LXT972M Transceiver device supports a programmable slew-rate mechanism whereby one of four pre-selected slew rates can be used. (For details, see Table 56, "Transmit Control Register Address 30, Hex 1E" on page 89.) The slew-rate mechanism allows the designer to optimize the output waveform to match the characteristics of the magnetics. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 49 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.8 10 Mbps Operation The LXT972M Transceiver operates as a standard 10BASE-T transceiver and supports standard 10 Mbps functions. During 10BASE-T operation, the LXT972M Transceiver transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT972M Transceiver drives link pulses onto the line. In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT972M Transceiver and sent across the MII to the MAC. Note: 5.8.1 10BASE-T Preamble Handling The LXT972M Transceiver offers two options for preamble handling, selected by Register bit 16.5. * In 10BASE-T mode when Register bit 16.5 = 0, the LXT972M Transceiver strips the entire preamble off of received packets. CRS is asserted coincident with the start of the preamble. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT972M Transceiver are the SFD "5D" hex followed by the body of the packet. * In 10BASE-T mode when Register bit 16.5 = 1, the LXT972M Transceiver passes the preamble through the MII and asserts RX_DV and CRS simultaneously. (In 10BASE-T loopback, the LXT972M Transceiver loops back whatever the MAC transmits to it, including the preamble.) 5.8.2 10BASE-T Carrier Sense For 10BASE-T links, CRS assertion is based on reception of valid preamble, and CRS de-assertion is based on reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion to be synchronized with RX_DV de-assertion. For details, see Table 51, "Configuration Register Address 16, Hex 10" on page 84. 5.8.3 10BASE-T Dribble Bits The LXT972M Transceiver handles dribble bits in all modes. If one to four dribble bits are received, the nibble is passed across the MII, padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus. 50 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.8.4 10BASE-T Link Integrity Test In 10BASE-T mode, the LXT972M Transceiver always transmits link pulses. * If the Link Integrity Test function is enabled (the normal configuration), the LXT972M Transceiver monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If the link pulses stop, the data transmission is disabled. * If the Link Integrity Test function is disabled (which can be done by setting Configuration Register bit 16.14 to `1'), the LXT972M Transceiver transmits to the connection regardless of detected link pulses. 5.8.5 Link Failure Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT972M Transceiver returns to the auto-negotiation phase if auto-negotiation is enabled. If the Link Integrity Test function is disabled by setting Configuration Register bit 16.14 to `1', the LXT972M Transceiver transmits packets, regardless of link status. 5.8.6 10BASE-T SQE (Heartbeat) By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972M Transceiver. To enable this function, set Register bit 16.9 = 1. When this function is enabled, the LXT972M Transceiver asserts its COL output for 5 to 15 bit times (BT) after each packet. 5.8.7 10BASE-T Jabber If a transmission exceeds the jabber timer, the LXT972M Transceiver disables the transmit and loopback functions. For jabber timing parameters, see Figure 26, "Intel(R) LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing" on page 69. The LXT972M Transceiver automatically exits jabber mode after the unjabber time has expired. This function can be disabled by setting Register bit 16.10 = 1. 5.8.8 10BASE-T Polarity Correction The LXT972M Transceiver automatically detects and corrects for the condition in which the receive signal (TPIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses - or four inverted end-of-frame (EOF) markers - are received consecutively. If link pulses or data are not received by the maximum receive time-out period (96 to 128 ms), the polarity state is reset to a non-inverted state. When polarity reversal is detected in 10BASE-T operation, register 17.5 is set to 1. (For details, see bit 17.5 in Table 52, "Status Register #2 - Address 17, Hex 11" on page 85.) Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 51 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.9 5.9.1 Monitoring Operations Monitoring Auto-Negotiation Auto-negotiation can be monitored as follows: * Register bit 17.7 is set to `1' once the auto-negotiation process is completed. * Register bits 1.2 and 17.10 are set to `1' once the link is established. * Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). Note: When the LXT972M Transceiver detects incorrect polarity for a 10BASE-T operation, Register bit 17.5 is set to `1'. 5.9.2 Monitoring Next Page Exchange The LXT972M Transceiver offers an Alternate Next Page mode to simplify the next page exchange process. Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled, Register bit 6.1 is automatically cleared whenever a new negotiation process takes place. This action prevents the user from reading an old value in bit 6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT972M Transceiver uses Register bit 6.5 to indicate when the current received page is the base page. This information is useful for recognizing when next pages must be resent due to a new negotiation process starting. Register bits 6.1 and 6.5 are cleared when read. 52 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.9.3 LED Functions The LXT972M Transceiver has these direct LED driver pins: LED/CFG1, LED/CFG2, and LED/ CFG3. On power-up, all the drivers are asserted for approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register (Table 54, "LED Configuration Register - Address 20, Hex 14" on page 87) to indicate one of the following conditions: * * * * * * Collision Condition Duplex Mode Link Status Operating Speed Receive Activity Transmit Activity The LED drivers can also be programmed to display various combined status conditions. For example, setting Register bits 20.15:12 to `1101' produces the following combination of Link and Activity indications: * If Link is down, LED is off. If activity is detected from the MAC, the LED still blinks even if the link is down. * If Link is up, LED is on. * If Link is up and activity is detected, the LED blinks at the stretch interval selected by Register bits 20.3:2 and continues to blink as long as activity is present. For the LXT972M Transceiver, the LED driver pins also provide initial configuration settings. The LED pins are sensitive to polarity and automatically pull up or pull down to configure for either open drain or open collector circuits (10 mA Max current rating) as required by the hardware configuration. For details, see the discussion of "Hardware Configuration Settings" on page 33. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 53 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.9.4 LED Pulse Stretching The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. The pulse stretch time is extended further if the event occurs again during this pulse stretch period. When an event such as receiving a packet occurs, the event is edge detected and it starts the stretch timer. The LED driver remains asserted until the stretch timer expires. If another event occurs before the stretch timer expires, then the stretch timer is reset and the stretch time is extended. When a long event (such as duplex status) occurs, the event is edge detected and it starts the stretch timer. When the stretch timer expires, the edge detector is reset so that a long event causes another pulse to be generated from the edge detector, which resets the stretch timer and causes the LED driver to remain asserted. Figure 18 shows how the stretch operation functions. Figure 18. LED Pulse Stretching Event LED stretch stretch stretch Note: The direct drive LED outputs in this diagram are shown as active L ow. B3475-01 54 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.10 Boundary Scan (JTAG 1149.1) Functions The LXT972M Transceiver includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. Note: For the related BSDL file, contact your local sales office or access the Intel website (www.intel.com). 5.10.1 Boundary Scan Interface The boundary scan interface consists of five pins (TMS, TDI, TDO, TRST_L, and TCK). It includes a state machine, data register array, and instruction register. The TMS and TDI pins are pulled up internally. TCK is pulled down internally. TDO does not have an internal pull-up or pulldown. 5.10.2 State Machine The TAP controller is a state machine, with 16 states driven by the TCK and TMS pins. Upon reset, the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are high for five TCK periods. 5.10.3 Instruction Register After the state machine resets, the IDCODE instruction is always invoked. The decode logic ensures the correct data flow to the Data registers according to the current instruction. Table 16 lists valid JTAG instructions for the LXT972M Transceiver. Table 16. Valid JTAG Instructions Name EXTEST IDCODE SAMPLE HIGHZ CLAMP BYPASS Code 1111 1111 1110 1000 1111 1111 1111 1110 1111 1111 1111 1000 1111 1111 1100 1111 1111 1111 1110 1111 1111 1111 1111 1111 Description External Test ID Code Inspection Sample Boundary Force Float Control Boundary to 1/0 Bypass Scan Test Mode Data Register BSR ID REG BSR Bypass Bypass Bypass Normal Normal Normal Test Normal Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 55 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.10.4 Boundary Scan Register Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. Table 17 lists the four BSR modes of operation. Table 17. BSR Mode of Operation Mode 1 2 3 4 Description Capture Shift Update System Function 5.10.5 Device ID Register Table 18 lists the bits for the Device ID register. For the current version of the JEDEC continuation characters, see the specification update for the LXT972M Transceiver. Table 18. Device ID Register for Intel(R) LXT972M Transceiver Bits 31:28 Version XXXX Bits 27:12 Part ID (Hex) 03CB Bits 11:8 JEDEC Continuation Characters 0000 Bits 7:1 JEDEC ID1 111 1110 Bit 0 Reserved 1 1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC ID is FE (1111 1110), which becomes 111 1110. 56 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 6.0 6.1 Application Information Magnetics Information The LXT972M Transceiver requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from static voltages across the connectors and cables. For transformer/magnetics requirements, see Table 19. Note: Before committing to a specific component, contact the manufacturer for current product specifications and validate the magnetics for the specific application. Table 19. Magnetics Requirements Parameter Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to common mode rejection 35 -16 Return Loss -10 - - dB 80 MHz - - - - dB dB 60 to 100 MHz 30 MHz Min - - 0.0 350 - 40 Nom 1:1 1:1 0.6 - 1.5 - Max - - 1.1 - - - Units - - dB H Test Condition - - - - - 0.1 to 60 MHz kV dB 6.2 Typical Twisted-Pair Interface Table 20 provides a comparison of the RJ-45 connections for NIC and Switch applications in a typical twisted-pair interface setting. Table 20. I/O Pin Comparison of NIC and Switch RJ-45 Setups RJ-45 Symbol Switch TPIP TPIN TPOP TPON 1 2 3 6 NIC 3 6 1 2 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 57 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 19 shows the LXT972M Transceiver in a typical twisted-pair interface, with the RJ-45 connections crossed over for a Switch configuration. Figure 19. Intel(R) LXT972M Transceiver Typical Twisted-Pair Interface - Switch 270 pF 5% TPIP 50 1% 0.01 F 50 1% 1:1 RJ-45 1 3 50 50 2 3 4 TPIN TPOP 270 pF 5% 1:1 50 Intel(R) LXT972M Transceiver TPON 5 6 2 0.1F 50 50 50 7 8 1 * * * = 0.001 F / 2.0 kV 4 VCCA 0.1F .01F GND B3515-02 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center tap from a 2.5 V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT972M Transceiver. 3. Magnetics without a receive pair center-tap do not require a 2 kV termination. 4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, see Figure 20 on page 59. 58 Document Number: 302875-005 Revision Date: 27-Oct-2005 To Twisted-Pair Network Datasheet Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 20 shows the LXT972M Transceiver in a typical twisted-pair interface, with the RJ-45 connections configured for a NIC application. Figure 20. Intel(R) LXT972M Transceiver Typical Twisted-Pair Interface - NIC RJ-45 270 pF 5% 50 50 8 7 50 1% 0.01 F 50 1% 1:1 6 3 50 50 50 5 4 3 TPIP Intel(R) LXT972M Transceiver TPON 270 pF 5% 1:1 2 2 0.1F 1 TPOP 1 4 * = 0.001 F / 2.0 kV * * VCCA 0.1F .01F GND SD/TP_L B3513-01 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center tap from a 2.5 V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT972M Transceiver. 3. Magnetics without a receive pair center tap do not require a 2 kV termination. 4. RJ-45 connections shown for standard NIC. TX/RX crossover may be required for repeater and switch applications. To Twisted-Pair Network TPIN 50 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 59 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 21 shows a typical media independent interface (MII) for the LXT972M Transceiver. Figure 21. Intel(R) LXT972M Transceiver Typical Media Independent Interface TX_EN TXD[3:0] TX_CLK RX_CLK MAC RX_DV RX_ER RXD[3:0] CRS COL Intel(R) LXT972M Transceiver Transformer RJ-45 B3480-02 60 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 7.0 Electrical Specifications This chapter includes test specifications for the LXT972M Transceiver. These specifications are guaranteed by test except where noted "by design". * Table 21 lists the absolute maximum ratings. * Table 22 lists the recommended operating conditions. * Table 23 through Table 39 list the minimum and maximum values that apply over the recommended operating conditions specified. 7.1 Electrical Parameters Table 21 lists absolute maximum ratings for the LXT972M Transceiver. Caution: * Exceeding the absolute maximum rating values may cause permanent damage. * Functional operation under these conditions is not implied. * Exposure to maximum rating conditions for extended periods may affect device reliability. Table 21. Absolute Maximum Ratings for Intel(R) LXT972M Transceiver Parameter Supply Voltage Storage Temperature Sym VCC TST Min -0.3 -65 Max 4.0 +150 Units V C Table 22 lists the recommended operating conditions for the LXT972M Transceiver. Table 22. Recommended Operating Conditions for Intel(R) LXT972M Transceiver Parameter Recommended operating temperature Recommended supply voltage2 - Analog and digital Recommended supply voltage - I/O VCC current - 100 BASE-TX VCC current - 10 BASE-T Hard Power Down Soft Power Down Auto-Negotiation 2 Sym TOPA Vcca, Vccd Vccio ICC ICC ICC Icc ICC Min 0 3.14 2.35 - - - - - Typ1 - 3.3 - 92 66 - 51 90 Max 70 3.45 3.45 110 82 1 - 110 Units C V V mA mA mA mA mA 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. Voltages are with respect to ground unless otherwise specified. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 61 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 23 lists digital I/O characteristics for all pins except the MII, XI/XO, and LED/CFG pins. Table 23. Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage Sym VIL VIH II VOL VOH Min - 2.0 -10 - 2.4 Typ2 - - - - - Max 0.8 - 10 0.4 - Units V V A Test Conditions - - 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA V V 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. Table 24 lists digital I/O characteristics for the MII pins. Table 24. Digital I/O Characteristics1 - MII Pins Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage VOH Driver output resistance (Line driver output enabled) RO RO 3 3 Sym VIL VIH II VOL VOH Min - 2.0 -10 - 2.2 2.0 - - Typ2 - - - - - - 100 100 Max 0.8 - 10 0.4 - - - - Units V V A Test Conditions - - 0.0 < VI < VCCIO IOL = 4 mA IOH = -4 mA, VCCIO = 3.3 V IOH = -4 mA, VCCIO = 2.5 V VCCIO = 2.5 V VCCIO = 3.3 V V V V 1. MII digital I/O pins are tolerant to 5 V inputs. 2. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 3. Parameter is guaranteed by design and not subject to production testing. 62 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 25 lists the I/O characteristics for the REFCLK/XI and XO pins. Table 25. I/O Characteristics - REFCLK/XI and XO Pins Parameter Input Low Voltage Input High Voltage Input Clock Frequency Tolerance2 Input Clock Duty Cycle Input Capacitance 2 Symbol VIL VIH f Min - 2.0 - 35 - Typ1 - - - - 3.0 Max 0.8 - Units V V ppm % pF Test Conditions - - - - - 100 65 - Tdc CIN 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. Parameter is guaranteed by design and not subject to production testing. Table 26 lists the I/O characteristics for the LXT972M Transceiver LED/CFG pins. Table 26. I/O Characteristics - LED/CFG Pins Parameter Input Low Voltage Input High Voltage Input Current Output Low Voltage Output High Voltage Symbol VIL VIH II VOL VOH Min - 2.0 -10 - 2.0 Typ - - - - - Max 0.8 - 10 0.4 - Units V V A Test Conditions - - 0 < VI < VCCIO IOL = 10 mA IOH = -10 mA V V Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 63 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 27 lists the 100BASE-TX characteristics. Table 27. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) Symbol VP Vss TRF TRFS DCD VOS - Min 0.95 98 3.0 - 35 - - Typ1 - - - - 50 - - Max 1.05 102 5.0 0.5 65 5 1.4 Units V % ns ns % % ns Test Conditions Note 2 Note 2 Note 2 Note 2 Offset from 16 ns pulse width at 50% of pulse peak - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 (+/-1%) resistor. Table 28 lists the 10BASE-T characteristics. Table 28. 10BASE-T Transceiver Characteristics Parameter Symbol Min Typ Max Units Test Conditions Transmitter Peak differential output voltage Transition timing jitter added by the MAU and PLS sections VOP 2.2 2.5 2.8 V With transformer, line replaced by 100 resistor After line model specified by IEEE 802.3 for 10BASE-T MAU - 0 2 11 ns Receiver Receive Input Impedance Differential Squelch Threshold ZIN VDS - 300 - 420 22 585 k mV - - Table 29 lists the 10BASE-T link integrity timing characteristics. Table 29. 10BASE-T Link Integrity Timing Characteristics Parameter Time Link Loss Receive Link Pulse Link Min Receive Timer Link Max Receive Timer Link Transmit Period Link Pulse Width Symbol TLL TLP TLR MIN TLR MAX Tlt Tlpw Min 50 2 2 50 8 60 Typ - - - - - - Max 150 7 7 150 24 150 Units ms Link Pulses ms ms ms ns Test Conditions - - - - - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 64 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 7.2 Timing Diagrams Figure 22. Intel(R) LXT972M Transceiver 100BASE-TX Receive Timing 0 ns 250 ns TPI t4 CRS t3 RX_DV t1 t2 RXD[3:0] RX_CLK t6 COL Note: Timing diagram depicts 4B mode. t5 t7 B3492-03 Table 30. Intel(R) LXT972M Transceiver 100BASE-TX Receive Timing Parameters Parameter RXD[3:0], RX_DV, RX_ER3 setup to RX_CLK High RXD[3:0], RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD[3:0], RX_DV Receive start of "J" to CRS asserted Receive start of "T" to CRS de-asserted Receive start of "J" to COL asserted Receive start of "T" to COL de-asserted Sym t1 t2 t3 t4 t5 t6 t7 Min 10 10 3 12 10 16 17 Typ1 - - - - - - - Max - - 5 16 17 22 20 Units2 ns ns BT BT BT BT BT Test Conditions - - - - - - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10-8 s or 10 ns. 3. RX_ER is not shown in the figure. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 65 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 23. Intel(R) LXT972M Transceiver 100BASE-TX Transmit Timing 0ns 250ns t1 TXCLK TX_EN t2 TXD[3:0] t5 TPO t3 CRS Note: Timing diagram depicts 4B mode. B3454-03 t4 Figure 23 does not show the TX_ER signal. . Table 31. Intel(R) LXT972M Transceiver 100BASE-TX Transmit Timing Parameters Parameter TXD[3:0], TX_EN setup to TX_CLK High TXD[3:0], TX_EN hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPO out (Tx latency) Symbol t1 t2 t3 t4 t5 Min 12 0 20 24 5.3 Typ1 - - - - - Max - - 24 28 5.7 Units2 ns ns BT BT BT Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10-8 s or 10 ns. 66 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 24. Intel(R) LXT972M Transceiver 10BASE-T Receive Timing RX_CLK t3 RXD, RX_DV, RX_ER t1 t2 t4 t5 CRS t6 TPI t9 COL t8 t7 B3457-01 Table 32. Intel(R) LXT972M Transceiver 10BASE-T Receive Timing Parameter RXD, RX_DV. Setup to RX_CLK High. RXD, RX_DV, RX_ER Hold from RX_CLK High TPIP/N in to RXD out (Rx latency) CRS asserted to RXD, RX_DV, RX_ER asserted RXD, RX_DV, RX_ER de-asserted to CRS de-asserted TPI in to CRS asserted TPI quiet to CRS de-asserted TPI in to COL asserted TPI quiet to COL de-asserted Sym t1 t2 t3 t4 t5 t6 t7 t8 t9 Min 10 10 4.2 5 0.3 2 6 1 5 Typ1 - - - - - - - - - Max - - 6.6 32 0.5 28 10 31 10 Units2 ns ns BT BT BT BT BT BT BT Test Conditions - - - - - - - - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10-7 s or 100 ns. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 67 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 25. Intel(R) LXT972M Transceiver 10BASE-T Transmit Timing TX_CLK t1 TXD, TX_EN t3 CRS t5 TPO t4 t2 B3461-01 Table 33. Intel(R) LXT972M Transceiver 10BASE-T Transmit Timing Parameter TXD, TX_EN, setup to TX_CLK High TXD, TX_EN, hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPO out (Tx latency) Symbol t1 t2 t3 t4 t5 Min 10 0 - - - Typ1 - - 2 1 72.5 Max - - - - - Units2 ns ns BT BT BT Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10-7 s or 100 ns. 68 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 26. Intel(R) LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing TX_EN t1 TXD t2 COL B3455-01 Table 34. Intel(R) LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing Parameter Maximum transmit time Unjabber time Symbol t1 t2 Min 20 250 Typ1 - - Max 150 750 Units ms ms Test Conditions - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 69 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 27. Intel(R) LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing TX_CLK TX_EN t1 COL t2 B3458-01 Table 35. Intel(R) LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration Symbol t1 t2 Min 0.65 0.5 Typ1 - - Max 1.6 1.5 Units us us Test Conditions - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 70 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 28. Intel(R) LXT972M Transceiver Auto-Negotiation and Fast Link Pulse Timing Clock Pulse Data Pulse Clock Pulse TPOP t1 t2 t3 B3464-01 t1 Figure 29. Intel(R) LXT972M Transceiver Fast Link Pulse Timing FLP Burst FLP Burst TPOP t4 t5 B3465-01 Table 36. Intel(R) LXT972M Transceiver Auto-Negotiation / Fast Link Pulse Timing Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width FLP burst to FLP burst Clock/Data pulses per burst Symbol t1 t2 t3 t4 t5 - Min - 55.5 123 - 8 17 Typ1 100 - - 2 12 - Max - 63.8 127 - 24 33 Units ns s s Test Conditions - - - - - - ms ms Each clock pulse or data pulse 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 71 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 30. Intel(R) LXT972M Transceiver MDIO Input Timing MDC t1 t2 MDIO Figure 31. Intel(R) LXT972M Transceiver MDIO Output Timing t4 MDC t3 MDIO Table 37. Intel(R) LXT972M Transceiver MDIO Timing Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, sourced by PHY MDC period Symbol t1 t2 t3 t4 Min 10 5 - 125 Typ1 - - - - Max - - 150 - Units ns ns ns ns Test Conditions - - - MDC = 8 MHz 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 72 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 32. Intel(R) LXT972M Transceiver Power-Up Timing v1 VCC MDIO, and so on t1 B3494-01 Table 38. Intel(R) LXT972M Transceiver Power-Up Timing Parameter Voltage threshold Power Up delay2 Symbol v1 t1 Min - - Typ1 2.9 - Max - 300 Units V s Test Conditions - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance. The PHY comes out of reset after a delay of no more than 300 s. System designers should consider this value as a minimum value. After threshold v1 is reached, the MAC should delay no less than 300 s before accessing the MDIO port. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 73 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 33. Intel(R) LXT972M Transceiver RESET_L Pulse Width and Recovery Timing t1 t2 MDIO, and so on RESET_L B3495-01 Table 39. Intel(R) LXT972M Transceiver RESET_L Pulse Width and Recovery Timing Parameter RESET_L pulse width RESET_L recovery delay 2 Symbol t1 t2 Min 10 - Typ1 - Max - 300 Units ns s Test Conditions - - 1. Typical values are at 25 C and are for design aid only, not guaranteed, and not subject to production testing. 2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed performance. The PHY comes out of reset after a delay of no more than 300 s. System designers should consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than 300 s before accessing the MDIO port. 74 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 8.0 Register Definitions - IEEE Base Registers This chapter includes definitions for the IEEE base registers used by the LXT972M Transceiver. Chapter 9.0, "Register Definitions - Product-Specific Registers" includes definitions of additional product-specific LXT972M Transceiver registers, which are defined in accordance with the IEEE 802.3 standard for adding unique device functions. The LXT972M Transceiver register set has multiple 16-bit registers. * Table 40 is a register set listing of the IEEE base registers. * Table 41 through Table 49 provide bit descriptions of the base registers (address 0 through 8), which are defined in accordance with the "Reconciliation Sublayer and Media Independent Interface" and "Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation" sections of the IEEE 802.3 standard. Table 40. Register Set for IEEE Base Registers Address 0 1 2 3 4 5 6 7 8 9 10 11 to 14 15 Control Register Status Register #1 PHY Identification Register 1 PHY Identification Register 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Base Page Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Auto-Negotiation Link Partner Next Page Receive Register 1000BASE-T/100BASE-T2 Control Register 1000BASE-T/100BASE-T2 Status Register Reserved Extended Status Register Register Name Bit Assignments See Table 41 See Table 42. See Table 43. See Table 44. See Table 45 See Table 46. See Table 47. See Table 48. See Table 49. Not Implemented Not Implemented Not Implemented Not Implemented Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 75 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 41 lists control register bits. Table 41. Control Register - Address 0, Hex 0 Bit 0.15 0.14 Reset Loopback Name Description 0 = Normal operation 1 = PHY reset 0 = Disable loopback mode 1 = Enable loopback mode 0.6 0 0.13 0 1 0 1 Speed Selected 10 Mbps 100 Mbps 1000 Mbps (not supported) Reserved Type 1 R/W SC R/W Default 0 0 0.13 Speed Selection 0 1 1 R/W Note 2 0.12 0.11 0.10 0.9 0.8 0.7 Auto-Negotiation Enable Power-Down Isolate Restart AutoNegotiation Duplex Mode Collision Test 0 = Disable auto-negotiation process 1 = Enable auto-negotiation process 0 = Normal operation 1 = Power-down 0 = Normal operation 1 = Electrically isolate PHY from MII 0 = Normal operation 1 = Restart auto-negotiation process 0 = Half-duplex 1 = Full-duplex 0 = Disable COL signal test 1 = Enable COL signal test X - 0.6 0 0.13 0 1 0 1 Speed Selected 10 Mbps 100 Mbps 1000 Mbps (not supported) Reserved R/W R/W R/W R/W SC R/W R/W Note 2 0 0 0 Note 2 0 0.6 Speed Selection 0 1 1 R/W 0 0.5:0 Reserved Write as `0'. Ignore on Read. R/W 00000 1. R/W = Read/Write SC = Self Clearing 2. Some bits have their default values determined at reset by hardware configuration pins. For default details for these bits, see Section 5.4.4, "Hardware Configuration Settings". 76 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 42 lists MII status register bits. Table 42. MII Status Register #1 - Address 1, Hex 1 Bit 1.15 1.14 Name 100BASE-T4 Not Supported 100BASE-X Full-Duplex Description 0 = PHY not able to perform 100BASE-T4 1 = PHY able to perform 100BASE-T4 0 = PHY not able to perform full-duplex 100BASE-X 1 = PHY able to perform full-duplex 100BASE-X 0 = PHY not able to perform half-duplex 100BASE-X 1 = PHY able to perform half-duplex 100BASE-X 0 = PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps in halfduplex 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to perform full-duplex 100BASE-T2 1 = PHY able to perform full-duplex 100BASE-T2 0 = PHY not able to perform half-duplex 100BASE-T2 1 = PHY able to perform half-duplex 100BASE-T2 0 = No extended status information in register 15 1 = Extended status information in register 15 Ignore when read. 0 = PHY cannot accept management frames with preamble suppressed 1 = PHY accepts management frames with preamble suppressed 0 = Auto-negotiation not complete 1 = Auto-negotiation complete 0 = No remote fault condition detected 1 = Remote fault condition detected 0 = PHY is not able to perform auto-negotiation 1 = PHY is able to perform auto-negotiation 0 = Link is down 1 = Link is up 0 = Jabber condition not detected 1 = Jabber condition detected 0 = Basic register capabilities 1 = Extended register capabilities Type 1 RO RO Default 0 1 1.13 100BASE-X Half-Duplex RO 1 1.12 10 Mbps Full-Duplex RO 1 1.11 10 Mbps Half-Duplex RO 1 1.10 100BASE-T2 FullDuplex Not Supported 100BASE-T2 HalfDuplex Not Supported RO 0 1.9 RO 0 1.8 1.7 Extended Status Reserved MF Preamble Suppression Auto-Negotiation complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability RO RO 0 0 1.6 RO 0 1.5 1.4 1.3 1.2 1.1 1.0 RO RO/LH RO RO/LL RO/LH RO 0 0 1 0 0 1 1. RO = Read Only LL = Latching Low LH = Latching High Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 77 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver For Table 43 and Table 44, see Figure 34. Table 43. PHY Identification Register 1 - Address 2, Hex 2 Bit 2.15:0 Name PHY ID Number Description The PHY identifier is composed of bits 3 through 18 of the Organizationally Unique Identifier (OUI). Type 1 RO Default 0013 hex 1. RO = Read Only Table 44. PHY Identification Register 2 - Address 3, Hex 3 Bit 3.15:10 3.9:4 Name PHY ID number Manufacturer's model number Description The PHY identifier is composed of bits 19 through 24 of the OUI. 6 bits containing manufacturer's part number. Type 1 RO RO Default 011110 001110 For current revision ID information, see the Specification Update. 3.3:0 Manufacturer's revision number 4 bits containing manufacturer's revision number. RO 1. RO = Read Only Figure 34. PHY Identifier Bit Mapping abc Organizationally Unique Identifier (QUI) rs x PHY ID Register #1 (Address 2) = 0013 15 000 0 0 0 0 000000 10 0 0 15 11 0 11 PHY ID Register #2 (Address 3) 10 9 110 001 4 110 3 00 0 00 00 20 7B 5 03 0 Note: The Intel OUI is 00207B hex Manufacturer's Model Number Revision Number B3504-01 78 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 45 lists auto-negotiation advertisement bits. Table 45. Auto-Negotiation Advertisement Register - Address 4, Hex 4 Bit 4.15 4.14 4.13 4.12 4.11 4.10 Name Next Page Reserved Remote Fault Reserved Asymmetric Pause Pause Description 0 = Port has no ability to send multiple pages. 1 = Port has ability to send multiple pages. Ignore when read. 0 = No remote fault. 1 = Remote fault. Write as `0'. Ignore on Read. Pause operation defined in IEEE 802.3 Standard, Clause 40 and 27 0 = Pause operation disabled. 1 = Pause operation enabled for full-duplex links 0 = 100BASE-T4 capability is not available. 1 = 100BASE-T4 capability is available. NOTE: The LXT972M Transceiver does not support 100BASE-T4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver can be switched in if this capability is desired. 0 = Port is not 100BASE-TX full-duplex capable. 1 = Port is 100BASE-TX full-duplex capable. 0 = Port is not 100BASE-TX capable. 1 = Port is 100BASE-TX capable. 0 = Port is not 10BASE-T full-duplex capable. 1 = Port is 10BASE-T full-duplex capable. 0 = Port is not 10BASE-T capable. 1 = Port is 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future auto-negotiation development. <11111> = Reserved for future auto-negotiation development. NOTE: Unspecified or reserved combinations must not be transmitted. Type 1 R/W RO R/W R/W R/W R/W Default 0 0 0 0 0 0 4.9 100BASE-T4 R/W 0 4.8 4.7 4.6 4.5 100BASE-TX full-duplex 100BASE-TX 10BASE-T full-duplex 10BASE-T R/W R/W R/W R/W Note 2 Note 2 Note 2 Note 2 4.4:0 Selector Field, S<4:0> R/W 00001 1. R/W = Read/Write RO = Read Only 2. Some bits have their default values determined at reset by hardware configuration pins. For default details for these bits, see Section 5.4.4, "Hardware Configuration Settings". Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 79 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 46 lists auto-negotiation link partner base page ability bits. Table 46. Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5 Bit 5.15 Name Next Page Description 0 = Link Partner has no ability to send multiple pages. 1 = Link Partner has ability to send multiple pages. 0 = Link Partner has not received Link Code Word from the LXT972M Transceiver. 1 = Link Partner has received Link Code Word from the LXT972M Transceiver. 0 = No remote fault. 1 = Remote fault. Ignore when read. Pause operation defined in IEEE 802.3 Standard, Clause 40 and 27. 0 = Link Partner is not Pause capable. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is Pause capable. 0 = Link Partner is not 100BASE-T4 capable. 1 = Link Partner is 100BASE-T4 capable. 0 = Link Partner is not 100BASE-TX full-duplex capable. 1 = Link Partner is 100BASE-TX full-duplex capable. 0 = Link Partner is not 100BASE-TX capable. 1 = Link Partner is 100BASE-TX capable. 0 = Link Partner is not 10BASE-T full-duplex capable. 1 = Link Partner is 10BASE-T full-duplex capable. 0 = Link Partner is not 10BASE-T capable. 1 = Link Partner is 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future auto-negotiation development. <11111> = Reserved for future auto-negotiation development. Unspecified or reserved combinations must not be transmitted. Type 1 RO Default 0 5.14 Acknowledge RO 0 5.13 5.12 Remote Fault Reserved Asymmetric Pause RO RO 0 0 5.11 RO 0 5.10 5.9 Pause 100BASE-T4 100BASE-TX Full-Duplex 100BASE-TX 10BASE-T Full-Duplex 10BASE-T RO RO 0 0 5.8 RO 0 5.7 5.6 5.5 RO RO RO 0 0 0 5.4:0 Selector Field S<4:0> RO 0 1. RO = Read Only 80 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 47 lists auto-negotiation expansion bits. Table 47. Auto-Negotiation Expansion - Address 6, Hex 6 Bit 6.15:6 Name Reserved Ignore when read. Description Type 1 RO Default 0 6.5 Base Page This bit indicates the status of the auto-negotiation variable base page. It flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links. This bit is used only if Register bit 16.1 (that is, Alternate NP feature) is set. 0 = Base page = False (base page not received) 1 = Base page = True (base page received) RO/LH 0 6.4 6.3 6.2 Parallel Detection Fault Link Partner Next Page Able Next Page Able 0 = Parallel detection fault has not occurred. 1 = Parallel detection fault has occurred. 0 = Link partner is not next page able. 1 = Link partner is next page able. 0 = Local device is not next page able. 1 = Local device is next page able. This bit is cleared on Read. If Register bit 16.1 is set, the Page Received bit is also cleared when either mr_page_rx = false or transmit_disable = true. RO/LH RO RO 0 0 1 6.1 Page Received 1 = Indicates a new page is received and the received code word is loaded into Register 5 (Base Pages) or Register 8 (Next Pages) as specified in Clause 28 of IEEE 802.3. 0 = Link partner is not auto-negotiation able. 1 = Link partner is auto-negotiation able. RO/LH 0 6.0 Link Partner A/N Able RO 0 1. RO = Read Only LH = Latching High Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 81 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 48 lists auto-negotiation next page transmit bits. Table 48. Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 Bit 7.15 7.14 7.13 Name Next Page (NP) Reserved Message Page (MP) Acknowledge 2 (ACK2) Description 0 = Last page 1 = Additional next pages follow Ignore when read. 0 = Register bits 7.10:0 are user defined. 1 = Register bits 7.10.0 follow IEEE message page format. 0 = Cannot comply with message 1 = Complies with message 0 = Previous value of the transmitted Link Code Word equalled logic one 1 = Previous value of the transmitted Link Code Word equalled logic zero If Register bits 7.13 = 0, Register bits 7.10:0 are userdefined. If Register bits 7.13 = 1, Register bits 7.10:0 follow IEEE message page format. Type 1 R/W RO R/W Default 0 0 1 7.12 R/W 0 7.11 Toggle (T) R/W 0 7.10:0 Message/ Unformatted Code Field R/W 00000000 001 1. RO = Read Only. R/W = Read/Write Table 49 lists auto-negotiation link partner next page receive bits. Table 49. Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 Bit 8.15 Name Next Page (NP) Description 0 = Link Partner has no additional next pages to send 1 = Link Partner has additional next pages to send 0 = Link Partner has not received Link Code Word from LXT972M Transceiver. 1 = Link Partner has received Link Code Word from LXT972M Transceiver. 0 = Register bits 8.10:0 are user defined. 1 = Register bits 8.10:0 follow IEEE message page format. 0 = Link Partner cannot comply with the message 1 = Link Partner complies with the message 0 = Previous value of transmitted Link Code Word equal to logic one 1 = Previous value of transmitted Link Code Word equal to logic zero If Register bit 8.13 = 0, Register bits 18.10:0 are user defined. If Register bit 8.13 = 1, Register bits 18.10:0 follow IEEE message page format. Type 1 RO Default 0 8.14 Acknowledge (ACK) RO 0 8.13 Message Page (MP) Acknowledge 2 (ACK2) RO 0 8.12 RO 0 8.11 Toggle (T) RO 0 8.10:0 Message/Unformatted Code Field RO 000000 0000 1. RO = Read Only. 82 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 9.0 Register Definitions - Product-Specific Registers This chapter includes definitions of product-specific LXT972M Transceiver registers that are defined in accordance with the IEEE 802.3 standard for adding unique device functions. (For definitions of the IEEE base registers used by the LXT972M Transceiver, see Chapter 8.0, "Register Definitions - IEEE Base Registers".) * Table 50 lists the register set of the product-specific registers. * Table 51 through Table 56 provide bit descriptions of the product-specific registers (address 17 through 30). Table 50. Register Set for Product-Specific Registers Address 16 17 18 19 20 21 22-25 26 27 28 29 30 31 Register Name Port Configuration Register Status Register #2 Reserved Status Change Register LED Configuration Register Reserved Reserved Digital Configuration Register Reserved Reserved Reserved Transmit Control Register Reserved Bit Assignments See Table 51 See Table 52 See Table 53 See Table 54 See Table 55 See Table 56 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 83 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 51 lists configuration bits. Table 51. Configuration Register - Address 16, Hex 10 Bit 16.15 16.14 16.13 16.12 16.11 16.10 16.9 Name Reserved Force Link Pass Transmit Disable Bypass Scrambler (100BASE-TX) Reserved Jabber (10BASE-T) SQE (10BASE-T) TP Loopback (10BASE-T) CRS Select (10BASE-T) Reserved Description Write as `0'. Ignore on Read. 0 = Normal operation 1 = Force Link pass 0 = Normal operation 1 = Disable Twisted Pair transmitter 0 = Normal operation 1 = Bypass Scrambler and Descrambler Write as `0'. Ignore on Read. 0 = Normal operation 1 = Disable Jabber Correction 0 = Disable Heart Beat 1 = Enable Heart Beat 0 = Normal operation 1 = Disable TP loopback during half-duplex operation 0 = Normal Operation 1 = CRS deassert extends to RX_DV deassert Write as `0'. Ignore on Read. Preamble Enable. 0 = Set RX_DV high coincident with SFD. 1 = Set RX_DV high and RXD = preamble when CRS is asserted. NOTE: Preamble is always enabled in 100 Mbps operation. Write as `0'. Ignore on Read. Write as `0'. Ignore on Read. 0 = Disable alternate auto negotiate next page feature. 1 = Enable alternate auto negotiate next page feature. This bit enables or disables the register bit 6.5 capability. Type 1 R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 16.8 R/W 0 16.7 16.6 R/W R/W 1 0 16.5 PRE_EN R/W 0 16.4:3 16.2 Reserved Reserved R/W R/W 00 0 16.1 Alternate NP feature R/W 0 16.0 Reserved Write as `0'. Ignore on Read. R/W 0 1. R/W = Read /Write 84 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 52 lists register #2 status bits. Table 52. Status Register #2 - Address 17, Hex 11 Bit 17.15 Name Reserved Always 0. Description Type 1 RO Default 0 17.14 10/100 Mode 0 = LXT972M Transceiver is not operating 100BASE-TX mode. 1 = LXT972M Transceiver is operating in 100BASE-TX mode. 0 = LXT972M Transceiver is not transmitting a packet. 1 = LXT972M Transceiver is transmitting a packet. 0 = LXT972M Transceiver is not receiving a packet. 1 = LXT972M Transceiver is receiving a packet. 0 = No collision. 1 = Collision is occurring. 0 = Link is down. 1 = Link is up. 0 = Half-duplex. 1 = Full-duplex. 0 = LXT972M Transceiver is in manual mode. 1 = LXT972M Transceiver is in auto-negotiation mode. 0 = Auto-negotiation process not completed. 1 = Auto-negotiation process completed. This bit is valid only when auto negotiate is enabled. The value is equivalent to the value of Register bit 1.5. Always 0. 0 = Polarity is not reversed. 1 = Polarity is reversed. NOTE: Polarity is not a valid status in 100 Mbps mode. 0 = The LXT972M Transceiver is not Pause capable. 1 = The LXT972M Transceiver is Pause capable. 0 = No error occurred 1 = Error occurred (Remote Fault, jabber, parallel detect fault) NOTE: The register bit is cleared when the registers that generate the error condition are read. Always 0. Always 0. Always 0. RO 0 17.13 Transmit Status RO 0 17.12 Receive Status RO 0 17.11 17.10 17.9 Collision Status Link Duplex Mode RO RO RO 0 0 0 17.8 Auto-Negotiation RO 0 17.7 Auto-Negotiation Complete RO 0 17.6 Reserved RO 0 17.5 Polarity RO 0 17.4 Pause R 0 17:3 Error RO 0 17:2 17:1 17.0 Reserved Reserved Reserved RO RO RO 0 0 0 1. RO = Read Only. R/W = Read/Write Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 85 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 53 lists status change bits. Table 53. Status Change Register - Address 19, Hex 13 Bit 19.15:9 19.8 19.7 Name Reserved Reserved ANDONE Ignore on Read. Ignore on Read. Description Type 1 RO RO RO/ SC Default N/A 0 N/A Auto-negotiation Status 0 = Auto-negotiation has not completed. 1 = Auto-negotiation has completed. Speed Change Status 19.6 SPEEDCHG 0 = A Speed Change has not occurred since last reading this register. 1 = A Speed Change has occurred since last reading this register. Duplex Change Status 19.5 DUPLEXCHG 0 = A Duplex Change has not occurred since last reading this register. 1 = A Duplex Change has occurred since last reading this register. Link Status Change Status 19.4 LINKCHG 0 = A Link Change has not occurred since last reading this register. 1 = A Link Change has occurred since last reading this register. Ignore on Read. Ignore on Read. Ignore on Read. Ignore on Read. RO/ SC 0 RO/ SC 0 RO/ SC 0 19.3 19.2 19.1 19.0 Reserved Reserved Reserved Reserved RO RO RO RO 0 0 0 0 1. R/W = Read/Write, RO = Read Only, SC = Self Clearing. 86 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 54 lists LED configuration bits. Table 54. LED Configuration Register - Address 20, Hex 14 (Sheet 1 of 2) Bit Name Description 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) 0101 = Display Duplex Status (Continuous) 0110 = Unused 0111 = Display Receive or Transmit Activity (Stretched) 1000 = Test mode - turn LED on (Continuous) 1001 = Test mode - turn LED off (Continuous) 1010 = Test mode - blink LED fast (Continuous) 1011 = Test mode - blink LED slow (Continuous) 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status 0011 = Display Collision Status 0100 = Display Link Status (Default) 0101 = Display Duplex Status 0110 = Unused 0111 = Display Receive or Transmit Activity 1000 = Test mode - turn LED on 1001 = Test mode - turn LED off 1010 = Test mode - blink LED fast 1011 = Test mode - blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused Type 1 Default 20.15:12 LED1 Programming bits R/W 0000 20.11:8 LED2 Programming bits R/W 0100 1. R/W = Read /Write. RO = Read Only. LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). Activity causes the LED to blink, regardless of the link status. 3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are approximations. Not guaranteed or production tested. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 87 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 54. LED Configuration Register - Address 20, Hex 14 (Sheet 2 of 2) Bit Name Description 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status (Default) 0011 = Display Collision Status 0100 = Display Link Status 0101 = Display Duplex Status 0110 = Unused 0111 = Display Receive or Transmit Activity 1000 = Test mode- turn LED on 1001 = Test mode- turn LED off 1010 = Test mode- blink LED fast 1011 = Test mode- blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused 00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms. 11 = Reserved. 0 = Disable pulse stretching of all LEDs. 1 = Enable pulse stretching of all LEDs. Write as `0'. Ignore on Read. Type 1 Default LED3 20.7:4 Programming bits R/W 0010 20.3:2 LEDFREQ5 R/W 00 20.1 20.0 PULSESTRETCH Reserved R/W R/W 1 0 1. R/W = Read /Write. RO = Read Only. LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). Activity causes the LED to blink, regardless of the link status. 3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are approximations. Not guaranteed or production tested. Table 55 lists digital configuration bits for the LXT972M Transceiver. Table 55. Digital Configuration Register - Address 26, Hex 1A Bit 26.15:12 26.11 26.10 26.9 Name Reserved MII Drive Strength Reserved Show Symbol Error Description Write as `0'. Ignore on Read. MII Drive Strength 0 = Normal MII drive strength 1 = Increase MII drive strength Write as `0'. Ignore on Read. Show Symbol Error 0 = Normal MII_RXER 1 = 100BASE-X Error Signal to MII_RxER Type 1 R/W R/W R/W R/W Default 0000 0 0 0 00000000 0 26.8:0 Reserved Write as `0'. Ignore on Read. RO 1. R/W = Read /Write, RO = Read Only 88 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 56 lists transmit control bits. Table 56. Transmit Control Register - Address 30, Hex 1E Bit 30.15:13 Name Reserved Description Write as `0'. Ignore on Read. Transmit Low Power 0 = Normal transmission. 1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission. Port Rise Time Control 00 = 3.0 ns (Default) 01 = 3.4 ns 10 = 3.9 ns 11 = 4.4 ns Ignore on Read. Type2 R/W Default 000 30.12 Transmit Low Power R/W 0 30.11:10 Port Rise Time Control1 R/W 00 30.9:0 Reserved R/W 0000000 000 1. Values are approximations and may vary outside indicated values based upon implementation loading conditions. Not guaranteed. 2. R/W = Read/Write 3. Latch State during Reset is based on the state of hardware configuration pins at RESET_L. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 89 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 10.0 Intel(R) LXT972M Transceiver Package Specifications Figure 35. Intel(R) LXT972M Transceiver LQFP Package Specifications 48-Pin Low-Profile Quad Flat Pack Part Number LXT972M - Temperature Range (0C to +70C) NOTE: The package figure is generic and used only to demonstrate package dimensions. NOTE: The 5.500 REF measure is from the center of first pin to the center of last pin. D C0.55 (in MM) X 45 Pin 1 D D1 D1 E1 E E1 3x C0.30 (in MM) X 45 5.500 REF (in MM) E B3813-01 Millimeters Dim A A1 A2 B D D1 E E1 e L L1 Min - 0.05 1.35 0.17 8.80 6.90 8.80 6.90 0.45 11o 0o Max 1.60 0.15 1.45 0.27 9.20 7.10 9.20 7.10 0.75 13o 7o e e/ 2 L1 A A1 L B 3 A2 3 0.50 BSC1 1.00 REF 3 1. Basic Spacing between Centers 90 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 5.500 R EF (in M M ) Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 10.1 Top Label Markings Figure 36 shows a sample LQFP package for the LXT972M Transceiver. Note: In contrast to the Pb-Free (RoHS-compliant) LQFP package, the non-RoHS-compliant package does not have the "e3" symbol in the last line of the package label. Figure 36. Sample LQFP Package - Intel(R) LXT972M Transceiver DJ972MA4 XXXXXXXX Part Number FPO Number Blank Line MC `YY Year Pin 1 B5294-01 Figure 37 shows a sample Pb-Free (RoHS-compliant) LQFP package for the LXT972M Transceiver. Figure 37. Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel(R) LX972M Transceiver WJ972MA4 XXXXXXXX Part Number FPO Number Blank Line MC ` YY e3 Pb-Free Indication Year Pin 1 B5295-01 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 91 Intel(R) LXT972M Single-Port 10/100 Mbps PHY Transceiver 11.0 Product Ordering Information Table 57 lists product ordering information for the LXT972M Transceiver. Table 57. Product Ordering Information Number DJLXT972MLC.A4 WJLXT972MLC.A4 Revision A4 A4 Package Type LQFP LQFP Pin Count 48 48 RoHS Compliant No Yes Figure 38 shows an order matrix with sample information for ordering an LXT972M Transceiver. Figure 38. Order Matrix for Intel(R) LXT972M Transceiver DJ LXT 972M L C A4 Product Revision xn = 2 Alphanumeric characters Temperature Range A = Ambient (0 - 550 C) C = Commercial (0 - 700 C) E = Extended (-40 - 85 0 C) Internal Package Designator L = LQFP P = PLCC N = DIP Q = PQFP H = QFP T = TQFP B = BGA C = CBGA E = TBGA K = HSBGA (BGA with heat slug Product Code xxxxx = 3-5 Digit alphanumeric IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device (MAC/Framer) IXP = Network processor Intel Package Designator B4863-02 92 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 |
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